3d semiconductor device and structure with nand logic

Abstract

A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a second level including a plurality of second transistors, where the second level overlays the first level, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the plurality of second transistors is at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

We claim: 
     
         1 . A 3D semiconductor device, the device comprising:
 a first level comprising a single crystal layer and a plurality of first transistors;   a first metal layer comprising interconnects between said plurality of first transistors,
 wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates; 
   a second level comprising a plurality of second transistors,
 wherein said second level overlays said first level, 
 wherein at least six of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, 
 wherein at least one of said plurality of second transistors is at least partially directly atop of said NAND logic structure; and 
   a second metal layer atop at least a portion of said second level,
 wherein said second level is bonded to said first level, and 
 wherein said bonded comprises oxide to oxide bonds. 
   
     
     
         2 . The 3D semiconductor device according to  claim 1 , further comprising:
 a third level overlaying said second level,
 wherein said third level comprises third transistors. 
   
     
     
         3 . The 3D semiconductor device according to  claim 1 , further comprising:
 a TSV through said single crystal layer to provide connection to an external device.   
     
     
         4 . The 3D semiconductor device according to  claim 1 ,
 wherein at least one of said plurality of first transistors is connected to a source of at least one of said plurality of second transistors.   
     
     
         5 . The 3D semiconductor device according to  claim 1 ,
 wherein at least one of said plurality of second transistors is a vertically oriented transistor.   
     
     
         6 . The 3D semiconductor device according to  claim 1 ,
 wherein said second metal layer is aligned to said first metal layer with less than 250 nm misalignment.   
     
     
         7 . The 3D semiconductor device according to  claim 1 ,
 wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain, and   wherein said source, said channel, and said drain comprise a same doping type.   
     
     
         8 . A 3D semiconductor device, the device comprising:
 a first level comprising a single crystal layer and a plurality of first transistors;   a first metal layer comprising interconnects between said plurality of first transistors,
 wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates; 
   a second level comprising a plurality of second transistors,
 wherein said second level overlays said first level, 
 wherein at least six of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, 
 wherein at least one of said plurality of second transistors is at least partially directly atop of said NAND logic structure; and 
   a second metal layer atop at least a portion of said second level,
 wherein six of said plurality of second transistors are directly connected to the same conductive line. 
   
     
     
         9 . The 3D semiconductor device according to  claim 8 , further comprising:
 a third level overlaying said second level,
 wherein said third level comprises third transistors. 
   
     
     
         10 . The 3D semiconductor device according to  claim 8 , further comprising:
 a TSV through said single crystal layer to provide connection to an external device.   
     
     
         11 . The 3D semiconductor device according to  claim 8 ,
 wherein at least one of said plurality of first transistors is connected to a source of at least one of said plurality of second transistors.   
     
     
         12 . The 3D semiconductor device according to  claim 8 ,
 wherein at least one of said plurality of second transistors is a vertically oriented transistor.   
     
     
         13 . The 3D semiconductor device according to  claim 8 ,
 wherein said second metal layer is aligned to said first metal layer with less than  250  nm misalignment.   
     
     
         14 . The 3D semiconductor device according to  claim 8 ,
 wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain, and   wherein said source, said channel, and said drain comprise a same doping type.   
     
     
         15 . A 3D semiconductor device, the device comprising:
 a first level comprising a single crystal layer and a plurality of first transistors;   a first metal layer comprising interconnects between said plurality of first transistors,
 wherein said interconnects between said plurality of first transistors comprise forming a plurality of logic gates; 
   a second level comprising a plurality of second transistors,
 wherein said second level overlays said first level, 
 wherein at least six of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, 
 wherein at least one of said plurality of second transistors is at least partially directly atop of said NAND logic structure; and 
   a second metal layer atop at least a portion of said second level,
 wherein said first level comprises a third metal layer atop at least a portion of said first metal layer, and 
 wherein said first metal layer is thicker than said third metal layer by at least 50%. 
   
     
     
         16 . The 3D semiconductor device according to  claim 15 , further comprising:
 a third level overlaying said second level,
 wherein said third level comprises third transistors. 
   
     
     
         17 . The 3D semiconductor device according to  claim 15 , further comprising:
 a TSV through said single crystal layer to provide connection to an external device.   
     
     
         18 . The 3D semiconductor device according to  claim 15 ,
 wherein at least one of said plurality of first transistors is connected to a source of at least one of said plurality of second transistors.   
     
     
         19 . The 3D semiconductor device according to  claim 15 ,
 wherein said second metal layer is aligned to said first metal layer with less than 250 nm misalignment.   
     
     
         20 . The 3D semiconductor device according to  claim 15 ,
 wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain, and   wherein said source, said channel, and said drain comprise a same doping type.