Flexible Diplexer with Dynamically Configurable Band-Split in Hybrid Fiber Coax Deployments

Abstract

A flexible diplexer may include a programmably reconfigurable filter pair capable of rendering a variety of band-split arrangements in a digital signal processor (DSP) backed design in hybrid fiber coaxial cable plant/system deployments. The flexible diplexers may thereby meet a larger range of band-split requirements, including the full range of band-split requirements. Configurability may be achieved by digitizing the signal at either input interface of a diplexer in a diplexer/amplifier complex after bandpass filtering, and two-to-four wire conversion at the respective forward (e.g. downstream) and reverse (e.g. upstream) input interfaces. A new band-split may be obtained by updating the digital filters using specified coefficient sets determined off-line and retrieved from memory. The flexible diplexer/amplifier complex may enable the implementation of additional functionality including equalization and tilt regeneration, self-interference cancellation, virtual segmentation, and/or creation of auxiliary service points to provide access to/from a small cell base station and/or Wi-Fi access point.

1 . A dynamically configurable diplexer, the diplexer comprising:
 an upstream input port and an upstream output port configured for upstream communications over a cable network;   a downstream input port and a downstream output port configured for downstream communications over the cable network; and   a pair of digital filters comprising a first digital filter coupling the upstream input port to the upstream output port and a second digital filter coupling the downstream input port to the downstream output port, wherein the pair of digital filters is programmably configurable to allocate a first portion of a total bandwidth of signals passing through the diplexer to the upstream communications and allocate a second portion of the total bandwidth to the downstream communications.   
     
     
         2 . The diplexer of  claim 1 , wherein the first digital filter is a digital low-pass filter and the second digital filter is a digital high-pass filter. 
     
     
         3 . The diplexer of  claim 1 , wherein the pair of digital filters are configured to operate according to a programmably configured set of filter coefficients. 
     
     
         4 . The diplexer of  claim 3 , wherein the programmably configured set of filter coefficients is retrieved from memory. 
     
     
         5 . The diplexer of  claim 1 , further comprising:
 a first analog-to-digital converter (ADC) configured convert an analog upstream signal received at the upstream input port to a corresponding digital upstream signal and provide the digital upstream signal to the first digital filter;   a second ADC configured convert a analog downstream signal received at the downstream input port to a corresponding digital downstream signal and provide the digital downstream signal to the second digital filter;   a first digital-to-analog converter (DAC) configured to convert a filtered digital upstream signal received from the first digital filter to a corresponding analog upstream signal and provide the analog upstream signal to the upstream output port; and   a second DAC configured to convert a filtered digital downstream signal received from the second digital filter to a corresponding analog downstream signal and provide the analog downstream signal to the downstream output port.   
     
     
         6 . The diplexer of  claim 1 , further comprising:
 a first amplifier configured to amplify an upstream signal of the upstream communications and provide the amplified upstream signal to the upstream output port; and   a second amplifier configured to amplify a downstream signal of the downstream communications and provide the amplified downstream signal to the downstream output port.   
     
     
         7 . The diplexer of  claim 1 , further comprising:
 control circuitry configured to perform operations comprising one or more of:
 equalization and tilt regeneration; 
 self-interference cancellation; or 
 signal reconditioning. 
   
     
     
         8 . The diplexer of  claim 7 , wherein the control circuit comprises:
 an analog echo cancellation stage configured to mitigate interfering downstream signal energy to suppress an impact of the interfering downstream signal energy on data conversion and/or on subsequent digital processing.   
     
     
         9 . The diplexer of  claim 8 , wherein the control circuit further comprises:
 a digital echo cancellation stage configured to mitigate residual interfering downstream signal energy that remains following mitigation performed by the analog echo cancellation stage.   
     
     
         10 . A network node station comprising:
 a bidirectional port for upstream and downstream communications; and   a diplexer comprising:
 an upstream input port and an upstream output port configured for upstream communications via the bidirectional port; 
 a downstream input port and a downstream output port configured for downstream communications via the bidirectional port; and 
 a pair of digital filters comprising a first digital filter coupling the upstream input port to the upstream output port and a second digital filter coupling the downstream input port to the downstream output port, wherein the pair of digital filters is programmably configurable to allocate a first portion of a total bandwidth of signals passing through the diplexer to the upstream communications and allocate a second portion of the total bandwidth to the downstream communications. 
   
     
     
         11 . The network node station of  claim 10 , wherein the pair of digital filters are configured to operate according to a programmably configured set of filter coefficients. 
     
     
         12 . The network node station of  claim 11 , wherein the programmably configured set of filter coefficients is retrieved from memory. 
     
     
         13 . The network node station of  claim 10 , further comprising:
 a first analog-to-digital converter (ADC) configured convert an analog upstream signal received at the upstream input port to a corresponding digital upstream signal and provide the digital upstream signal to the first digital filter;   a second ADC configured convert a analog downstream signal received at the downstream input port to a corresponding digital downstream signal and provide the digital downstream signal to the second digital filter;   a first digital-to-analog converter (DAC) configured to convert a filtered digital upstream signal received from the first digital filter to a corresponding analog upstream signal and provide the analog upstream signal to the upstream output port; and   a second DAC configured to convert a filtered digital downstream signal received from the second digital filter to a corresponding analog downstream signal and provide the analog downstream signal to the downstream output port.   
     
     
         14 . The network node station of  claim 10 , further comprising:
 a first amplifier configured to amplify an upstream signal of the upstream communications and provide the amplified upstream signal to the upstream output port; and   a second amplifier configured to amplify a downstream signal of the downstream communications and provide the amplified downstream signal to the downstream output port.   
     
     
         15 . The network node station of  claim 10 , further comprising:
 control circuitry configured to perform operations comprising one or more of:
 equalization and tilt regeneration; 
 self-interference cancellation; or 
 signal reconditioning. 
   
     
     
         16 . The network node station of  claim 15 , wherein the control circuit comprises:
 an analog echo cancellation stage configured to mitigate interfering downstream signal energy to suppress an impact of the interfering downstream signal energy on data conversion and/or on subsequent digital processing.   
     
     
         17 . The network node station of  claim 16 , wherein the control circuit further comprises:
 a digital echo cancellation stage configured to mitigate residual interfering downstream signal energy that remains following mitigation performed by the analog echo cancellation stage.   
     
     
         18 . A wired communication device, comprising:
 a non-transitory computer-readable memory medium;   one or more processors communicatively coupled to the non-transitory computer-readable memory medium; and   a diplexer configured to facilitate upstream and downstream communications of the wired communication device, the diplexer comprising:
 an upstream input port and an upstream output port configured for the upstream communications; 
 a downstream input port and a downstream output port configured for the downstream communications; and 
 a pair of digital filters comprising a first digital filter coupling the upstream input port to the upstream output port and a second digital filter coupling the downstream input port to the downstream output port, wherein the pair of digital filters is programmably configurable to allocate a first portion of a total bandwidth of signals passing through the diplexer to the upstream communications and allocate a second portion of the total bandwidth to the downstream communications. 
   
     
     
         19 . The wired communication device of  claim 18 , wherein the diplexer further comprises:
 an analog echo cancellation stage configured to mitigate interfering downstream signal energy to suppress an impact of the interfering downstream signal energy on data conversion and/or on subsequent digital processing.   
     
     
         20 . The wired communication device of  claim 19 , wherein the diplexer further comprises:
 a digital echo cancellation stage configured to mitigate residual interfering downstream signal energy that remains following mitigation performed by the analog echo cancellation stage.