Packaged Semiconductor Device With Multilayer Stress Buffer

Abstract

In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound.

What is claimed is: 
     
         1 . A packaged semiconductor device (PSD), comprising:
 a semiconductor die with a component proximate to a surface of the semiconductor die;   the semiconductor die mounted on a substrate;   the component covered with a first polymer layer with a first modulus;   at least a portion of the first polymer layer covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus; and   the semiconductor die and a portion of the substrate covered with mold compound.   
     
     
         2 . The PSD of  claim 1 , wherein sidewalls of the first polymer layer and the second polymer layer are convex. 
     
     
         3 . The PSD of  claim 1 , wherein the first polymer layer and the second polymer layer are straight, within 20 degrees of vertical. 
     
     
         4 . The PSD of  claim 2 , wherein the first polymer layer has straight, within 20 degrees of vertical sidewalls, and the second polymer layer has convex sidewalls. 
     
     
         5 . The PSD of  claim 1 , wherein the first polymer layer covers the component and covers the surface of the semiconductor die surrounding the component to a distance of at least 20 μm. 
     
     
         6 . The PSD of  claim 5 , wherein the first modulus is between 0.1 GPa and 1 GPa and the second modulus is between 2 and 4 GPa. 
     
     
         7 . The PSD of  claim 5 , wherein a first thickness of the first polymer layer is between 5 μm and 20 μm, a second thickness of the second polymer layer is between 2 μm and 10 μm, and the sum of the first thickness and the second thickness is between 10 μm and 30 μm. 
     
     
         8 . The PSD of  claim 5 , wherein the first polymer layer is one selected from a group consisting essentially of: a silicone, a bismaleimide, an epoxy, and wherein the second polymer layer is one selected from a group consisting essentially of: a polyimide, a polybenzoxazole (PBO), an epoxy-based polymer, and negative photoresist SU8. 
     
     
         9 . The PSD of  claim 5 , wherein the second polymer layer is a metal/polymer composite with a modulus between 6 GPa and 9 GPa. 
     
     
         10 . The PSD of  claim 9 , wherein the metal/polymer composite is one selected from a group consisting essentially of: a polyimide resin filled with metal nanoparticles;
 a polyimide resin filled with metal coated ceramic nanoparticles; an epoxy resin filled with metal nanoparticles; and an epoxy resin filled with metal coated ceramic nanoparticles.   
     
     
         11 . The PSD of  claim 10  wherein the metal in the metal nanoparticles is one selected from a group consisting essentially of: gold, silver, and copper. 
     
     
         27 . A packaged semiconductor device (PSD), comprising:
 a semiconductor die on a substrate;   a first polymer layer having a first modulus less than 1 GPa and the first polymer layer covering a component that is proximate to a surface of the semiconductor die and covering the component and the surface of the semiconductor die surrounding the component to a distance of at least 20 μm;   a second polymer layer having a second modulus greater than 1 GPa and the second polymer layer covering at least a portion of the first polymer layer;   a mold compound covering the semiconductor die and a portion of the substrate.   
     
     
         28 . The PSD of  claim 27 , wherein the first modulus is between 0.1 to 1 GPa and the second modulus is between 2 and 4 GPa. 
     
     
         29 . The PSD of  claim 27 , wherein the first polymer layer has a thickness between 5 μm and 20 μm, and the second polymer layer has a thickness between 2 μm and 10 μm. 
     
     
         30 . The PSD of  claim 27 , wherein the first layer is ink jet deposited. 
     
     
         31 . The PSD of  claim 27 , wherein the component is located within the semiconductor die proximate a surface of the semiconductor die. 
     
     
         32 . The PSD of  claim 27 , wherein the component is located on the surface of the semiconductor die. 
     
     
         33 . The PSD of  claim 27 , wherein the component is located at a surface of the semiconductor die. 
     
     
         34 . The PSD of  claim 27 , wherein the component is formed at an initial surface of the semiconductor die and then covered by layers of conductors and insulating dielectric layers. 
     
     
         35 . The PSD of  claim 27 , wherein the component is located within the semiconductor die proximate a surface of the semiconductor die.