Semiconductor devices

Abstract

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to enable a start signal and an oscillation signal based on the reset signal. The oscillation signal starts to oscillate in response to the reset signal.

1 - 17 . (canceled) 
     
     
         18 . A semiconductor device comprising:
 a first rank configured to perform a memory access operation; and   a second rank configured to perform a termination operation while the first rank performs the memory access operation.   
     
     
         19 . The semiconductor device of  claim 18 ,
 wherein the memory access operation and the termination operation are performed simultaneously.   
     
     
         20 . The semiconductor device of  claim 18 ,
 wherein the first rank is configured to operate in synchronization with a clock signal in response to a first rank selection signal.   
     
     
         21 . The semiconductor device of  claim 18 ,
 wherein the first rank is configured to perform the memory access operation when successive values of the first rank selection that are sampled during two successive edges of the clock signal have changed.   
     
     
         22 . The semiconductor device of  claim 18 ,
 wherein the second rank is configured to operate in synchronization with a clock signal in response to a second rank selection signal.   
     
     
         23 . The semiconductor device of  claim 18 ,
 wherein the second rank is configured to block an internal control operation when the second rank performs the termination operation.   
     
     
         24 . The semiconductor device of  claim 18 ,
 wherein the second rank is configured to block an internal control operation when successive values of the second rank selection that are sampled during two successive edges of the clock signal have been maintained.   
     
     
         25 . The semiconductor device of  claim 18 ,
 wherein the second rank is configured to generate a command for execution of an internal control operation and a termination command for execution of the termination operation based on a second rank selection signal.   
     
     
         26 . The semiconductor device of  claim 18 ,
 wherein the second rank is configured to generate a termination command and terminate generation of a command when the second rank selection signal is enabled during an Nth period of a clock signal.   
     
     
         27 . A semiconductor device comprising:
 a rank configured to operate in synchronization with a clock signal in response to a rank selection signal and configured to transmit data;   an on-die termination circuit configured to prevent distortion of the data; and   a switch configured to control the on-die termination circuit in response to an internal signal that is related to the clock signal and the rank selection signal.   
     
     
         28 . The semiconductor device of  claim 27 ,
 wherein the switch is configured to transmit a signal that controls an operation of the on-die termination circuit.   
     
     
         29 . The semiconductor device of  claim 27 ,
 wherein the switch is configured to transmit a signal that turns on the on-die termination circuit.   
     
     
         30 . The semiconductor device of  claim 27 ,
 wherein the switch is configured to transmit a signal that turns off the on-die termination circuit during an initialization operation of the semiconductor device.   
     
     
         31 . The semiconductor device of  claim 27 ,
 wherein the on-die termination circuit is configured to perform an on-die termination operation when a value of the rank selection that is sampled by a first edge of the clock signal and a value of the rank selection that is sampled by a second edge of the clock signal both have an enabled state.   
     
     
         32 . The semiconductor device of  claim 27 ,
 wherein the rank is configured to perform a memory access operation when successive values of the rank selection that are sampled during two successive edges of the clock signal have changed.   
     
     
         33 . The semiconductor device of  claim 27 ,
 wherein the rank is configured to block an internal control operation when the rank performs a termination operation.   
     
     
         34 . The semiconductor device of  claim 27 ,
 wherein the rank is configured to block an internal control operation when successive values of the rank selection that are sampled during two successive edges of the clock signal have been maintained.   
     
     
         35 . The semiconductor device of  claim 27 , further comprising:
 another rank is configured to perform a memory access operation while the rank performs a termination operation.   
     
     
         36 . The semiconductor device of  claim 27 ,
 wherein the rank is configured to generate a command for execution of an internal control operation and a termination command for execution of a termination operation based on the rank selection signal.   
     
     
         37 . The semiconductor device of  claim 27 ,
 wherein the rank is configured to generate a termination command and terminate generation of a command when the rank selection signal is enabled during an Nth period of the clock signal.