Channel sizing for inter-kernel communication

Abstract

Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

1 . (canceled) 
     
     
         2 . A tangible, non-transitory, computer-readable medium, comprising computer-readable instructions that, when executed by a computer, cause the computer to:
 receive a high-level code comprising a representation of a producer kernel, a representation of a consumer kernel, and an indication to communicatively couple an output of the producer kernel to an input of the consumer kernel;   in response to receiving the high-level code, convert the high-level code into low-level code to be implemented on an integrated circuit (IC), the low-level code comprising a hardware implementation of the producer kernel, a hardware implementation of the consumer kernel, and a hardware implementation of a connection between the output of the producer kernel and the input of consumer kernel, wherein the hardware implementation of the connection does not access global memory of the IC; and   cause implementation of the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection in a programmable region of the IC.   
     
     
         3 . The tangible, non-transitory, computer-readable medium of  claim 2 , wherein the connection comprises a first in first out (FIFO) buffer. 
     
     
         4 . The tangible, non-transitory, computer-readable medium of  claim 3 , comprising instructions that, when executed by the computer, cause the computer to:
 size a depth of the FIFO buffer.   
     
     
         5 . The tangible, non-transitory, computer-readable medium of  claim 4 , comprising instructions that, when executed by the computer, cause the computer to:
 receive, during compilation, an indication of a desired depth of the FIFO buffer; and   size the depth based upon the desired depth.   
     
     
         6 . The tangible, non-transitory, computer-readable medium of  claim 5 , wherein the desired depth is based upon identifying potential stalls in the FIFO buffer. 
     
     
         7 . The tangible, non-transitory, computer-readable medium of  claim 2 , wherein the IC comprises a field programmable gate array (FPGA). 
     
     
         8 . The tangible, non-transitory, computer-readable medium of  claim 7 , wherein the FPGA comprises one or more interconnects and the programmable region comprises a plurality of programmable logic cells coupled via the one or more interconnects. 
     
     
         9 . The tangible, non-transitory, computer-readable medium of  claim 8 , wherein the global memory is external from the FPGA. 
     
     
         10 . The tangible, non-transitory, computer-readable medium of  claim 7 , wherein the programmable region of the IC comprises on-chip memory of the FPGA. 
     
     
         11 . The tangible, non-transitory, computer-readable medium of  claim 2 , comprising instructions, that when executed by the computer, cause the computer to:
 cause implementation of the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection in one or more partial reconfiguration regions of the IC.   
     
     
         12 . The tangible, non-transitory, computer-readable medium of  claim 2 , comprising instructions that, when executed by the computer, cause the computer to:
 cause data to stream from the output of the producer kernel to the input of the consumer kernel via the connection, independent of transmission of the data to other memory.   
     
     
         13 . A system comprising:
 an integrated circuit (IC) comprising one or more programmable regions configured to:
 receive a hardware implementation of a producer kernel, a hardware implementation of a consumer kernel, and a hardware implementation of a connection between an output of the producer kernel and an input of the consumer kernel, wherein the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection between the output of the producer kernel and the input of the consumer kernel are derived from high-level code comprising a representation of a producer kernel, a representation of a consumer kernel, and an indication to communicatively couple the output of the producer kernel and the input of the consumer kernel; and 
 implement and execute the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection in the one or more programmable regions, wherein the hardware implementation of the connection does not access global memory of the IC; and 
   a host, comprising a computer processor configured to execute a host program that offloads tasks from the host for completion by the IC.   
     
     
         14 . The system of  claim 13 , wherein the computer processor and the IC are connected via a peripheral component interconnect express (PCIe) interface. 
     
     
         15 . The system of  claim 13 , wherein the IC comprises a field programmable gate array (FPGA). 
     
     
         16 . The system of  claim 15 , wherein the FPGA comprises one or more interconnects and the programmable region comprises a plurality of programmable memory cells coupled via the one or more interconnects. 
     
     
         17 . The system of  claim 15 , wherein the programmable region of the IC comprises on-chip memory of the FPGA. 
     
     
         18 . The system of  claim 13 , wherein the IC is configured to implement the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection in one or more partial reconfiguration regions of the IC. 
     
     
         19 . The system of  claim 13 , wherein the connection comprises a first in first out (FIFO) buffer. 
     
     
         20 . The system of  claim 19 , wherein the FIFO buffer is sized based upon identifying potential stalls in FIFO buffer. 
     
     
         21 . The system of  claim 13 , wherein the IC is configured to cause data to stream from the output of the producer kernel to the input of the consumer kernel via the connection, independent of transmission of the data to other memory. 
     
     
         22 . The system of  claim 13 , comprising:
 a compiler configured to generate the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection between the output of the producer kernel and the input of the consumer kernel based upon the high-level code comprising the representation of a producer kernel, the representation of the consumer kernel, and the indication to communicatively couple the output of the producer kernel   
     
     
         23 . Field Programmable Gate Array (FPGA) circuitry, comprising:
 an interface; and   one or more programmable regions configurable to:
 receive, via the interface, a hardware implementation of a producer kernel, a hardware implementation of a consumer kernel, and a hardware implementation of a connection between an output of the producer kernel and an input of the consumer kernel, wherein the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection between the output of the producer kernel and the input of the consumer kernel are derived from high-level code comprising a representation of a producer kernel, a representation of a consumer kernel, and an indication to communicatively couple the output of the producer kernel and the input of the consumer kernel; and 
 implement and execute the hardware implementation of the producer kernel, the hardware implementation of the consumer kernel, and the hardware implementation of the connection in the one or more programmable regions, wherein the hardware implementation of the connection does not access global memory of the FPGA circuitry. 
   
     
     
         24 . The FPGA circuitry of  claim 23 , wherein the interface comprises a peripheral component interconnect express (PCIe) interface coupled to a host. 
     
     
         25 . The FPGA circuitry of  claim 23  comprising one or more interconnects and the programmable region comprises a plurality of programmable logic cells coupled via the one or more interconnects. 
     
     
         26 . The FPGA circuitry of  claim 23 , wherein the one or more programmable regions comprises on-chip memory of the FPGA. 
     
     
         27 . The FPGA circuitry of  claim 23 , wherein the one or more programmable regions comprises one or more partial reconfiguration regions. 
     
     
         28 . The FPGA circuitry of  claim 23 , wherein the connection comprises a first in first out (FIFO) buffer. 
     
     
         29 . The FPGA circuitry of  claim 28 , configured to:
 size a depth of the FIFO buffer.   
     
     
         30 . The FPGA circuitry of  claim 29 , wherein the size of the depth is based upon potential stalls in the FIFO buffer. 
     
     
         31 . The FPGA circuitry of  claim 23 , wherein the one or more programmable regions are configured to:
 receive data from a host device; and   supply the data to the producer kernel for processing.   
     
     
         32 . The FPGA circuitry of  claim 23 , wherein the one or more programmable regions comprise block random access memory (block RAM) and wherein the hardware implementation of the connection is implemented at least partially in the block RAM.