Charging an input capacitor of a load control device

Abstract

A load control device for controlling the amount of power delivered to an electrical load may include a rectifier circuit configured to receive a phase-control voltage and produce a rectified voltage. A power converter may be configured to receive the rectified voltage at an input and generate a bus voltage. An input capacitor may be coupled across the input of the power converter. The input capacitor may be adapted to charge when the magnitude of the phase control voltage is approximately zero volts. The power converter may be configured to operate in a boost mode, such that the magnitude of the bus voltage is greater than a peak magnitude of the input voltage. The power converter may be configured to operate in a buck mode to charge the input capacitor from the bus voltage when the magnitude of the phase-control voltage is approximately zero volts.

What is claimed is: 
     
         1 . An electrical load control apparatus, comprising:
 a controllably conductive device to receive an alternating current (AC) supply voltage; and   phase-control circuitry communicatively coupled to the memory circuitry and the controllably conductive device, the phase-control circuitry to:
 selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a phase controlled alternating current (AC) output voltage; 
 generate a reference edge in a first half-cycle of the AC output voltage contemporaneous with a first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states; and 
 select one of a plurality of offset times to generate one of a corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with a second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states;
 wherein each of the plurality of offset times corresponds to a different, unique, binary value. 
 
   
     
     
         2 . The electrical load control apparatus of  claim 1 :
 wherein the phase-controlled AC voltage consists of a forward phase-control AC voltage;   wherein the controllably conductive device generates the reference edge contemporaneous with the first transition from the NON-CONDUCTIVE state to the CONDUCTIVE state; and   wherein the controllably conductive device generates the reference edge contemporaneous with the second transition from the NON-CONDUCTIVE state to the CONDUCTIVE state.   
     
     
         3 . The electrical load control apparatus of  claim 1 :
 wherein the phase-controlled AC voltage consists of a reverse phase-control AC voltage;   wherein the controllably conductive device generates the reference edge contemporaneous with the first transition from the CONDUCTIVE state to the NON-CONDUCTIVE state; and   wherein the controllably conductive device generates the reference edge contemporaneous with the second transition from the CONDUCTIVE state to the NON-CONDUCTIVE state.   
     
     
         4 . The electrical load control apparatus of  claim 1  wherein the plurality of offset times corresponds to 2 n  discrete offset times and the different, unique binary values correspond to 2 n  different, unique, binary sequences. 
     
     
         5 . The electrical load control apparatus of  claim 4  wherein n=2. 
     
     
         6 . The electrical load control apparatus of  claim 5 , the control circuitry to:
 generate a 20-bit data frame transmitted over 10 AC cycles.   
     
     
         7 . The electrical load control apparatus of  claim 6  wherein to generate the 20-bit data frame, the control circuitry to further:
 generate a 4-bit start sequence field; 
 generate a 4-bit channel mask field; 
 generate a 2-bit command field; 
 generate a 5-bit data field; and 
 generate a 5-bit error detect field. 
 
     
     
         8 . An electrical load control method, comprising:
 selectively transitioning, by phase-control circuitry, a controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a phase controlled alternating current (AC) output voltage;   generating, by the phase-control circuitry, a reference edge in a first half-cycle of the AC output voltage contemporaneous with a first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states; and   selecting, by the phase-control circuitry, one of a plurality of offset times to generate one of a corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with a second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states;   wherein each of the plurality of offset times corresponds to a different, unique, binary value.   
     
     
         9 . The method of  claim 8 :
 wherein selectively transitioning the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further comprises:   selectively transitioning, by the phase-control circuitry, the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a forward phase-control AC voltage;   wherein generating the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:   generating, by the phase-control circuitry, the reference edge contemporaneous with the first transition from the NON-CONDUCTIVE state to the CONDUCTIVE state; and   wherein generating one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:   generating, by the phase-control circuitry, the reference edge contemporaneous with the second transition from the NON-CONDUCTIVE state to the CONDUCTIVE state.   
     
     
         10 . The method of  claim 8 :
 wherein selectively transitioning the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further comprises:   selectively transitioning, by the phase-control circuitry, the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a reverse phase-control AC voltage;   wherein generating the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:   generating, by the phase-control circuitry, the reference edge contemporaneous with the first transition from the CONDUCTIVE state to the NON-CONDUCTIVE state; and   wherein generating one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:   generating, by the phase-control circuitry, the reference edge contemporaneous with the second transition from CONDUCTIVE state to the NON-CONDUCTIVE state.   
     
     
         11 . The method of  claim 8  wherein selecting one of the plurality of offset times to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage further comprises:
 selecting, by the phase-control circuitry, one of 2 n  discrete offset times to generate a respective data edge at each of the 2 n  discrete offset times in the second half-cycle of the AC output voltage to provide 2 n  binary sequences, each corresponding to one of the 2 n  offset times. 
 
     
     
         12 . The method of  claim 11  wherein selecting one of 2 n  discrete offset times to generate the respective data edge at each of the 2 n  discrete offset times in the second half-cycle of the AC output voltage to provide 2 n  binary sequences, each corresponding to one of the 2 n  offset times further comprises:
 selecting, by the phase-control circuitry, one of 2 2  discrete offset times to generate a respective data edge at each of the 2 2  discrete offset times in the second half-cycle of the AC output voltage to provide 2 2  binary sequences, each corresponding to one of the 2 2  offset times. 
 
     
     
         13 . The method of  claim 12 , further comprising:
 generating, by the phase-control circuitry, a 20-bit data frame transmitted over 10 AC cycles.   
     
     
         14 . The method of  claim 13  wherein generating the 20-bit data frame transmitted over 10 AC cycles further comprises:
 generating, by the phase-control circuitry, a 4-bit start sequence field; 
 generating, by the phase-control circuitry, a 4-bit channel mask field; 
 generating, by the phase-control circuitry, a 2-bit command field; 
 generating, by the phase-control circuitry, a 5-bit data field; and 
 generating, by the phase-control circuitry, a 5-bit error detect field. 
 
     
     
         15 . A non-transitory, machine-readable, storage device that includes instructions that, when executed by phase-control circuitry, causes the phase-control circuitry to:
 selectively transition a controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a phase controlled alternating current (AC) output voltage;   generate a reference edge in a first half-cycle of the AC output voltage contemporaneous with a first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states; and   select one of a plurality of offset times to generate one of a corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with a second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states;   wherein each of the plurality of offset times corresponds to a different, unique, binary value.   
     
     
         16 . The non-transitory, machine-readable, storage device of  claim 15 :
 wherein the instructions that cause the phase-control circuitry to selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further cause the phase-control circuitry to:
 selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a forward phase-control AC voltage; 
 wherein the instructions that cause the phase-control circuitry to generate the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the phase-control circuitry to: 
 generate the reference edge contemporaneous with the first transition from the NON-CONDUCTIVE state to the CONDUCTIVE state; and 
 wherein the instructions that cause the phase-control circuitry to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the control circuitry to: 
 generate the reference edge contemporaneous with the second transition from the NON-CONDUCTIVE state to the CONDUCTIVE state. 
   
     
     
         17 . The non-transitory, machine-readable, storage device of  claim 15 :
 wherein the instructions that cause the phase-control circuitry to selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further cause the phase-control circuitry to:
 selectively transitioning, by the phase-control circuitry, the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a reverse phase-control AC voltage; 
   wherein the instructions that cause the phase-control circuitry to generate the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the phase-control circuitry to:
 generate the reference edge contemporaneous with the first transition from the CONDUCTIVE state to the NON-CONDUCTIVE state; and 
   wherein the instructions that cause the phase-control circuitry to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the control circuitry to:
 generate the reference edge contemporaneous with the second transition from CONDUCTIVE state to the NON-CONDUCTIVE state. 
   
     
     
         18 . The non-transitory, machine-readable, storage device of  claim 15  wherein the instructions that cause the phase-control circuitry to select one of the plurality of offset times to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage further cause the phase-control circuitry to:
 select one of 2 n  discrete offset times to generate a respective data edge at each of the 2 n  discrete offset times in the second half-cycle of the AC output voltage to provide 2 n  binary sequences, each corresponding to one of the 2 n  offset times. 
 
     
     
         19 . The non-transitory, machine-readable, storage device of  claim 18  wherein the instructions that cause the phase-control circuitry to select one of 2 n  discrete offset times to generate the respective data edge at each of the 2 n  discrete offset times in the second half-cycle of the AC output voltage to provide 2 n  binary sequences, each corresponding to one of the 2 n  offset times further cause the phase-control circuitry to:
 select one of 2 2  discrete offset times to generate a respective data edge at each of the 2 2  discrete offset times in the second half-cycle of the AC output voltage to provide 2 2  binary sequences, each corresponding to one of the 2 2  offset times. 
 
     
     
         20 . The non-transitory, machine-readable, storage device of  claim 19  wherein the instructions further cause the phase-control circuitry to:
 generate a 20-bit data frame transmitted over 10 AC cycles. 
 
     
     
         21 . The non-transitory, machine-readable, storage device of  claim 20  wherein the instructions that cause the phase-control circuitry to generate the 20-bit data frame transmitted over 10 AC cycles further cause the phase-control circuitry to:
 generate a 4-bit start sequence field; 
 generate a 4-bit channel mask field; 
 generate a 2-bit command field; 
 generate a 5-bit data field; and 
 generate a 5-bit error detect field.