Active device substrate

Abstract

A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.

What is claimed is: 
     
         1 . An active device substrate, comprising
 a substrate having an active region and a peripheral region;   a first insulation layer located on the substrate;   a second insulation layer located on the first insulation layer;   a first active device located on the active region, wherein the first active device comprises a first crystallized metal oxide layer;   a second active device located on the peripheral region, wherein the second active device comprises a second crystallized metal oxide layer, and the first crystallized metal oxide layer and the second crystallized metal oxide layer are both in contact with the first insulation layer; and   a third active device located on the peripheral region and electrically connected to the second active device, wherein the third active device comprises a P-type doped silicon semiconductor layer, and the second insulation layer is located between the P-type doped silicon semiconductor layer and the first insulation layer.   
     
     
         2 . The active device substrate of  claim 1 , wherein
 the first active device comprises:
 a first gate overlapped with the first crystallized metal oxide layer in a direction perpendicular to the substrate, and 
 a first source and a first drain electrically connected to the first crystallized metal oxide layer; and 
   the second active device comprises:
 a second gate overlapped with the second crystallized metal oxide layer in the direction perpendicular to the substrate, and 
 a second source and a second drain electrically connected to the second crystallized metal oxide layer. 
   
     
     
         3 . The active device substrate of  claim 2 , further comprises:
 a third insulation layer, disposed on and in contact with a top surface of the first gate, a top surface of the second gate, and a top surface of the P-type doped silicon semiconductor layer, wherein the third insulation layer is located between a third gate of the third active device and the P-type doped silicon.   
     
     
         4 . The active device substrate of  claim 2 , wherein:
 the third active device comprises a third gate, and the P-type doped silicon semiconductor layer is located between the second crystallized metal oxide layer and the third gate.   
     
     
         5 . The active device substrate of  claim 4 , wherein the P-type doped silicon semiconductor layer and the second crystallized metal oxide layer are located between the third gate and the second gate. 
     
     
         6 . The active device substrate of  claim 1 , wherein the P-type doped silicon semiconductor layer and the second crystallized metal oxide layer are overlapped in a direction perpendicular to the substrate. 
     
     
         7 . The active device substrate of  claim 1 , wherein
 the first crystallized metal oxide layer comprises an indium element, a gallium element, a zinc element, and an oxygen element, and   the second crystallized metal oxide layer comprises an indium element, a gallium element, a tin element, and an oxygen element.   
     
     
         8 . The active device substrate of  claim 1 , wherein a material of the first insulation layer and the second insulation layer comprises silicon oxide. 
     
     
         9 . The active device substrate of  claim 1 , wherein a material of the first crystallized metal oxide layer is different material with a material of the second crystallized metal oxide layer, a bottom surface of the first crystallized metal oxide layer and a bottom surface of the second crystallized metal oxide layer are in contact with the first insulation layer. 
     
     
         10 . The active device substrate of  claim 9 , wherein a top surface of the first crystallized metal oxide layer and a top surface of the second crystallized metal oxide layer are in contact with the second insulation layer. 
     
     
         11 . The active device substrate of  claim 10 , wherein a bottom surface of the P-type doped silicon semiconductor layer is in contact with the second insulation layer. 
     
     
         12 . The active device substrate of  claim 1 , wherein the second insulation layer is a patterned layer which is not overlapping the first active device and the second active device in a direction perpendicular to the substrate. 
     
     
         13 . The active device substrate of  claim 12 , wherein:
 the third active device comprises a third source and a third drain connected with sidewalls of the second insulation layer and sidewalls of the P-type doped silicon semiconductor layer.   
     
     
         14 . The active device substrate of  claim 1 , wherein the first crystallized metal oxide layer and the second crystallized metal oxide layer are crystallized using a laser process. 
     
     
         15 . The active device substrate of  claim 14 , wherein the first crystallized metal oxide layer and the second crystallized metal oxide layer are both clamped between the first insulation layer and the second insulation layer, and wherein the first insulation layer and the second insulation layer are configured as heat preservation layers in the laser process.