Method for implementing a line speed interconnect structure

Abstract

A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

1 . A method for pipeline speed computer instruction processing, comprising:
 receiving a plurality of computer instructions;   performing a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions;   performing combining and splitting of the plurality of computer instructions by a second stage; and   forwarding the plurality of computer instructions to a next processing stage in the pipeline at pipeline speed.   
     
     
         2 . The method of  claim 1 , wherein the first stage performs position shuffling, pairing, and splitting of the computer instructions based on a destination of each of the plurality of computer instructions. 
     
     
         3 . The method of  claim 1 , wherein the combining combines microinstructions of the plurality of computer instructions that have a same destination next stage of the pipeline. 
     
     
         4 . The method of  claim 1 , wherein the splitting splits computer instructions that have a different destination next stage of the pipeline. 
     
     
         5 . The method of  claim 1 , wherein the plurality of computer instructions are each composed of at least one microinstruction. 
     
     
         6 . The method of  claim 1 , wherein computer instructions that exceed a given number of microinstructions are split into at least two computer instructions. 
     
     
         7 . A processor device, comprising:
 a scheduler to select from a plurality of computer instructions for dispatch;   a pipeline to process the computer instructions; and   a remapper coupled to the scheduler and pipeline, the remapper configured to
 receive the plurality of computer instructions, perform a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions, perform combining and splitting of the plurality of computer instructions by a second stage, and forwarding the plurality of computer instructions to a next processing stage in the pipeline at pipeline speed. 
   
     
     
         8 . The processor of  claim 7 , wherein the first stage performs position shuffling, pairing, and splitting of the computer instructions based on a destination of each of the plurality of computer instructions. 
     
     
         9 . The processor of  claim 7 , wherein the combining combines microinstructions of the plurality of computer instructions that have a same destination next stage of the pipeline. 
     
     
         10 . The processor of  claim 7 , wherein the splitting splits computer instructions that have a different destination next stage of the pipeline. 
     
     
         11 . The processor of  claim 7 , wherein the plurality of computer instructions are each composed of at least one microinstruction. 
     
     
         12 . The processor of  claim 7 , wherein computer instructions that exceed a given number of microinstructions are split into at least two computer instructions. 
     
     
         13 . A computer system, comprising:
 a main memory; and   a processor coupled to the main memory, the processor including a remapper, the remapper configured to   receive a plurality of computer instructions, perform a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions, perform combining and splitting of the plurality of computer instructions by a second stage, and forwarding the plurality of computer instructions to a next processing stage in a pipeline at pipeline speed.   
     
     
         14 . The computer system of  claim 13 , wherein the first stage of the remapper performs position shuffling, pairing, and splitting of the computer instructions based on a destination of each of the plurality of computer instructions. 
     
     
         15 . The computer system of  claim 13 , wherein the combining combines microoperations of the plurality of computer instructions that have a same destination next stage of the pipeline. 
     
     
         16 . The computer system of  claim 13 , wherein the splitting splits computer instructions that have a different destination next stage of the pipeline. 
     
     
         17 . The computer system of  claim 13 , wherein the plurality of computer instructions are each composed of at least one microoperation. 
     
     
         18 . The computer system of  claim 13 , wherein computer instructions that exceed a given number of microoperations are split into at least two computer instructions.