US2021341963A1PendingUtilityA1
Data strobe multiplexer
Est. expiryJun 28, 2038(~11.9 yrs left)· nominal 20-yr term from priority
Inventors:Claudio GiaccioFerdinando PascaleErminio Di MartinoRaffaele MastrangeloFerdinando D'AlessandroAndrea CastaldoCristiano Castellano
Y02D10/00G06F 13/1689G06F 13/4243G06F 1/12G11C 7/1066G06F 13/4054G06F 13/4022
60
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
Claims
exact text as granted — not AI-modified1 . (canceled)
2 . A system comprising:
a host device; and a multiplexer circuit configured to receive a data signal and a data strobe signal from an embedded MultiMediaCard (eMMC) device, and to selectively provide one of the data signal or the data strobe signal to a data pin of the host device, wherein the host device is configured to receive an output of the multiplexer circuit at the data pin of the host device, and wherein the host device is configured to:
determine a timing relationship between the data strobe signal received from the multiplexer circuit at the data pin of the host device and an internal clock signal in a calibration mode; and
control sampling of the data signal received from the multiplexer circuit at the data pin of the host device using the determined timing relationship in a data read mode.
3 . The system of claim 2 , wherein the data pin is one of a set of data pins (DAT[N: 0 ]), wherein N is a positive integer.
4 . The system of claim 3 , wherein the host device includes:
a command pin (CMD); a clock pin (CLK); a general-purpose input/output (GPIO) pin; and the data pin, and wherein the host device does not include a dedicated data strobe pin.
5 . The system of claim 2 , wherein the host device is configured to:
provide a command to the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device; provide a control signal, separate from the command to the eMMC device, to the multiplexer circuit to provide the data strobe signal from the eMMC device at the output of the multiplexer circuit; and receive the data strobe signal from the output of the multiplexer circuit at the data pin of the host device, wherein the multiplexer circuit is separate from the eMMC device.
6 . The system of claim 2 , wherein the host device includes:
a delay circuit configured to delay the received output of the multiplexer circuit from the data pin by a configurable delay value; and a sampling circuit configured to sample the output of the multiplexer circuit at a transition of the internal clock signal, wherein, to determine the timing relationship in the calibration mode, the host device is configured to adjust the delay value of the delay circuit and to sample the output of the multiplexer circuit at different delay values to determine an alignment between the output of the multiplexer circuit and the internal clock signal.
7 . The system of claim 2 , including the eMMC device, wherein the data pin of the eMMC device is coupled to the data pin of the host device and the eMMC device includes a dedicated data strobe pin configured to provide the data strobe signal in a high-speed mode, and
wherein the multiplexer circuit includes:
a first input coupled to the data pin of the eMMC device configured to receive read data from the eMMC device;
a second input coupled to the data strobe pin of the eMMC device configured to receive the data strobe signal from the eMMC device;
an output coupled to the data pin of the host device; and
a control input coupled to a general-purpose input/output (GPIO) pin of the host device.
8 . The system of claim 2 , wherein, in the calibration mode, the host device is configured to:
provide a control signal to the multiplexer circuit using a general-purpose input/output (GPIO) pin of the host device; and provide a read command to the eMMC device configured to trigger the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device.
9 . The system of claim 8 , wherein, in the data read mode, the host device is configured to:
provide a control signal to the multiplexer circuit using the GPIO pin to couple the data pin of the eMMC device to the output of the multiplexer circuit; provide a read command to the eMMC device; and receive read data from the multiplexer circuit at the data pin of the host device.
10 . The system of claim 8 , wherein, in the data read mode, the multiplexer circuit is configured to receive the data strobe signal from the eMMC device, but is not configured to provide the data strobe signal to the host device,
wherein the eMMC device includes a dedicated data strobe pin, and wherein the host device does not include a dedicated data strobe pin.
11 . The system of claim 2 , wherein the host device is configured to intermittently trigger the calibration mode to determine the timing relationship between the data strobe signal and the internal clock signal, and to control a delay value of a delay circuit using the determined timing relationship.
12 . A method comprising:
receiving, at a multiplexer circuit, a data signal and a data strobe signal from an embedded MultiMediaCard (eMMC) device, and selectively providing, using the multiplexer circuit, one of the data signal or the data strobe signal to a data pin of a host device; determining, using the host device, a timing relationship between the data strobe signal received from the multiplexer circuit at the data pin of the host device and an internal clock signal in a calibration mode; and controlling, using the host device, sampling of the data signal received from the multiplexer circuit at the data pin of the host device using the determined timing relationship in a data read mode.
13 . The method of claim 12 , wherein the data pin is one of a set of data pins (DAT[N: 0 ]), wherein N is a positive integer.
14 . The method of claim 13 , wherein the host device includes:
a command pin (CMD); a clock pin (CLK); a general-purpose input/output (GPIO) pin; and the data pin, and wherein the host device does not include a dedicated data strobe pin.
15 . The method of claim 12 , comprising:
providing, using the host device, a command to the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device; providing, using the host device, a control signal, separate from the command to the eMMC device, to the multiplexer circuit to provide the data strobe signal from the eMMC device at the output of the multiplexer circuit; and receiving the data strobe signal from the output of the multiplexer circuit at the data pin of the host device, wherein the multiplexer circuit is separate from the eMMC device.
16 . The method of claim 12 , comprising:
delaying the received output of the multiplexer circuit from the data pin by a configurable delay value using a delay circuit; and sampling the output of the multiplexer circuit at a transition of the internal clock signal using a sampling circuit, wherein determining the timing relationship in the calibration mode comprises adjusting the delay value of the delay circuit and sampling the output of the multiplexer circuit at different delay values to determine an alignment between the output of the multiplexer circuit and the internal clock signal.
17 . The method of claim 12 , wherein the data pin of the eMMC device is coupled to the data pin of the host device and the eMMC device includes a dedicated data strobe pin configured to provide the data strobe signal in a high-speed mode,
wherein the method includes:
receiving read data from the eMMC device using a first input of the multiplexer circuit coupled to the data pin of the eMMC device; and
receiving the data strobe signal from the eMMC device using a second input of the multiplexer circuit coupled to the data strobe pin of the eMMC device, and
wherein the multiplexer circuit includes:
an output coupled to the data pin of the host device; and
a control input coupled to a general-purpose input/output (GPIO) pin of the host device.
18 . The method of claim 12 , comprising, in the calibration mode, using the host device:
providing a control signal to the multiplexer circuit using a general-purpose input/output (GPIO) pin of the host device; and providing a read command to the eMMC device configured to trigger the eMMC device to provide the data strobe signal on the data strobe pin of the eMMC device.
19 . The method of claim 18 , comprising, in the data read mode, using the host device:
providing a control signal to the multiplexer circuit using the GPIO pin to couple the data pin of the eMMC device to the output of the multiplexer circuit; providing a read command to the eMMC device; and receiving read data from the multiplexer circuit at the data pin of the host device.
20 . The method of claim 18 , comprising, in the data read mode:
receiving the data strobe signal from the eMMC device using the multiplexer circuit, but not providing the data strobe signal to the host device, wherein the eMMC device includes a dedicated data strobe pin, and wherein the host device does not include a dedicated data strobe pin.
21 . The method of claim 12 , comprising:
intermittently triggering the calibration mode to determine the timing relationship between the data strobe signal and the internal clock signal and to control a delay value of a delay circuit using the determined timing relationship.Join the waitlist — get patent alerts
Track US2021341963A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.