US2021335660A1PendingUtilityA1

Semiconductor structure having void between bonded wafers and manufacturing method tehreof

Assignee: NANYA TECHNOLOGY CORPPriority: Apr 24, 2020Filed: Apr 24, 2020Published: Oct 28, 2021
Est. expiryApr 24, 2040(~13.7 yrs left)· nominal 20-yr term from priority
Inventors:Hsih-Yang Chiu
H10W 20/0265H10W 20/2134H10W 20/0242H10W 20/0234H10W 20/0253H10P 95/04H10W 20/081H10W 72/01H10W 72/0198H10W 72/90H10W 20/023H10W 20/435H10W 20/20H10W 20/069H10W 20/056H10W 20/074H10W 90/00H10W 20/42H10D 84/0193H10D 84/038H01L 21/823821H01L 21/32115H01L 21/76829H01L 21/76814
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Claims

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer including a first dielectric layer and a first component disposed within the first dielectric layer; a second wafer disposed over the first wafer and including a second dielectric layer over the first dielectric layer, and a second component within the second dielectric layer; and a conductive structure including a first member surrounded by the first dielectric layer and the second dielectric layer, and a second member protruding from the first member and surrounded by the second wafer. A method of manufacturing the semiconductor structure is also provided.

Claims

exact text as granted — not AI-modified
1 . A semiconductor structure, comprising:
 a first wafer including a first dielectric layer and a first component disposed within the first dielectric layer;   a second wafer disposed over the first wafer and including a second dielectric layer over the first dielectric layer, and a second component within the second dielectric layer; and   a conductive structure including a first member surrounded by the first dielectric layer and the second dielectric layer, and a second member protruding from the first member and surrounded by the second wafer, wherein the first member of the conductive structure includes a first part surrounded by the first dielectric layer and a second part surrounded by the second dielectric layer, wherein a portion of the first part is contacted with the second dielectric layer, or a portion of the second part is contacted with the first dielectric layer.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first dielectric layer is in contact with the second dielectric layer. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first component, the second component and the conductive structure are electrically connected to each other. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the first component and the second component at least partially contact the first member of the conductive structure. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein a thickness of the first wafer is substantially greater than a thickness of the second wafer. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the first dielectric layer and the second dielectric layer include oxide. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising an isolating layer surrounding at least a portion of the second member of the conductive structure and disposed between the second dielectric layer and the second member of the conductive structure. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein the isolating layer includes oxide. 
     
     
         9 . A method of manufacturing a semiconductor structure, comprising:
 providing a first wafer including a first substrate, a first dielectric layer disposed over the first substrate, and a first component formed within the first dielectric layer;   providing a second wafer including a second substrate, a second dielectric layer disposed over the second substrate, and a second component formed within the second dielectric layer; removing a first portion of the first dielectric layer to form a first recess;   removing a second portion of the second dielectric layer to form a second recess;   disposing the second wafer over the first wafer to bond the first dielectric layer to the second dielectric layer;   removing a third portion of the second substrate and the second dielectric layer to form a third recess coupled to the second recess; and   disposing a conductive material to fill the first recess, the second recess and the third recess to form a conductive structure.   
     
     
         10 . The method of  claim 9 , wherein the removal of the first portion of the first dielectric layer includes exposing a portion of the first component through the first dielectric layer. 
     
     
         11 . The method of  claim 10 , wherein the removal of the second portion of the second dielectric layer includes exposing a portion of the second component through the second dielectric layer. 
     
     
         12 . The method of  claim 9 , wherein the first recess is aligned with the second recess. 
     
     
         13 . The method of  claim 9 , wherein a void defined by the first recess and the second recess is formed after the disposing of the second wafer over the first wafer. 
     
     
         14 . The method of  claim 9 , wherein the removal of the third portion of the second substrate and the second dielectric layer includes removing a first section of the third portion to form a first opening, disposing an isolating layer conformal to the first opening, removing a bottom portion of the isolating layer, and removing a second section of the third portion to form a second opening. 
     
     
         15 . The method of  claim 9 , wherein the conductive material is disposed by electroplating. 
     
     
         16 . The method of  claim 9 , wherein the third portion of the second substrate and the second dielectric layer is removed by dry etching or laser drilling. 
     
     
         17 . The method of  claim 9 , wherein the disposing of the second wafer over the first wafer includes forming a first interface between the first dielectric layer and the second dielectric layer. 
     
     
         18 . The method of  claim 9 , wherein a second interface between the conductive structure and the first dielectric layer or a third interface between the conductive structure and the second dielectric layer is formed after the disposing of the conductive material. 
     
     
         19 . The method of  claim 9 , further comprising grinding the second substrate to reduce a thickness of the second wafer prior to the removal of the third portion of the second substrate and the second dielectric layer. 
     
     
         20 . The method of  claim 9 , wherein the first recess and the second recess are filled with the conductive material after the first dielectric layer is bonded to the second dielectric layer.

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