Memory with non-volatile configurations for efficient power management and operation of the same

Abstract

A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.

What is claimed is: 
     
         1 . A memory device, comprising:
 a memory array; and   circuitry configured to:
 store one or more memory training settings for the memory array in a non-volatile memory location; and 
 in response to returning to a powered-on state from a reduced-power state, read the one or more memory training settings from the non-volatile memory location. 
   
     
     
         2 . The memory device of  claim 1 , wherein the circuitry is further configured, in response to returning to the powered-on state from the reduced-power state, to read the one or more memory training settings from the non-volatile memory location without performing a memory training operation to determine the one or more memory training settings. 
     
     
         3 . The memory device of  claim 1 , wherein the one or more memory training settings are configured to place a memory data strobe within a data eye for a given memory cycle of the memory array by establishing one or more programmable latencies for the memory array and adjusting one or more timings for the memory array. 
     
     
         4 . The memory device of  claim 1 , wherein the one or more memory training settings include a read timing setting, a write timing setting, a CMD/CTL/ADDR timing setting, an ODT setting, a voltage setting, a latency setting, a ZQ calibration, an RCOMP resistance, or a combination thereof. 
     
     
         5 . The memory device of  claim 1 , wherein the circuitry is further configured to cause the memory device to enter the reduced-power state in response to receiving a command from a connected host device. 
     
     
         6 . The memory device of  claim 1 , wherein the circuitry is further configured to cause the memory device to enter the reduced-power state in response to a determination that the memory device is idle. 
     
     
         7 . The memory device of  claim 1 , wherein the circuitry is further configured to cause the memory device to return to the powered-on state from the reduced-power state in response to receiving a command from a connected host device. 
     
     
         8 . The memory device of  claim 1 , wherein the reduced-power state corresponds to a disconnection of at least a portion of the memory array from an applied voltage. 
     
     
         9 . The memory device of  claim 1 , wherein a single semiconductor chip comprises the circuitry and the memory array. 
     
     
         10 . The memory device of  claim 1 , wherein a first semiconductor chip comprises the circuitry and a second one or more semiconductor chips comprise the memory array. 
     
     
         11 . A method of operating a memory device including a memory array, the method comprising:
 storing one or more memory training settings for the memory array in a non-volatile memory location; and   in response to returning to a powered-on state from a reduced-power state, reading the one or more memory training settings from the non-volatile memory location.   
     
     
         12 . The method of  claim 11 , further comprising:
 in response to returning to the powered-on state from the reduced-power state, reading the one or more memory training settings from the non-volatile memory location without performing a memory training operation to determine the one or more memory training settings.   
     
     
         13 . The method of  claim 11 , wherein the one or more memory training settings are configured to place a memory data strobe within a data eye for a given memory cycle of the memory array by establishing one or more programmable latencies for the memory array and adjusting one or more timings for the memory array. 
     
     
         14 . The method of  claim 11 , wherein the one or more memory training settings include a read timing setting, a write timing setting, a CMD/CTL/ADDR timing setting, an ODT setting, a voltage setting, a latency setting, a ZQ calibration, an RCOMP resistance, or a combination thereof. 
     
     
         15 . The method of  claim 11 , further comprising:
 entering the reduced-power state in response to a determination that the memory device is idle.   
     
     
         16 . The method of  claim 15 , further comprising:
 returning to the powered-on state from the reduced-power state in response to receiving a command from a connected host device.   
     
     
         17 . A memory system, comprising:
 a host device; and   a memory device including a memory array operably coupled to the host device, the memory device configured to:
 store one or more settings for the memory array in a non-volatile memory location; and 
 in response to returning to a powered-on state from a reduced-power state, read the one or more memory training settings from the non-volatile memory location. 
   
     
     
         18 . The memory system of  claim 17 , wherein the memory device is further configured to, in response to returning to the powered-on state from the reduced-power state, communicate the one or more memory training settings to the host device after reading the one or more memory training settings from the non-volatile memory location. 
     
     
         19 . The memory system of  claim 17 , wherein the memory device is further configured to enter the reduced-power state in response to receiving a command from the host device. 
     
     
         20 . The memory system of  claim 17 , wherein the memory device is further configured to return to the powered-on state from the reduced-power state in response to receiving a command from the host device.