Semiconductor device and electronic device

Abstract

A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.

What is claimed is: 
     
         1 . A semiconductor device comprising a plurality of circuits arranged in an array:
 wherein each of the plurality of the circuits comprises:
 a first channel formation region; 
 a first insulating layer over the first channel formation region; 
 a first gate electrode over the first insulating layer, the first gate electrode overlapping with the first channel formation region; 
 a second insulating layer over the first gate electrode; 
 a third insulating layer over the second insulating layer, the third insulating layer is configured to block hydrogen; 
 a fourth insulating layer over the third insulating layer; 
 a second channel formation region over the fourth insulating layer, a semiconductor layer comprising the second channel formation region; 
 a fifth insulating layer over the second channel formation region; 
 a second gate electrode over the fifth insulating layer, the second gate electrode overlapping with the second channel formation region; 
 a third gate electrode directly connected to the second gate electrode, wherein the second gate electrode and the third gate electrode overlap with each other with the second channel formation region therebetween; and 
 a sixth insulating layer over the second gate electrode, the sixth insulating layer having an opening, wherein the opening overlaps with a first region of the semiconductor layer; 
 a first metal layer over the sixth insulating layer and in the opening, the first metal layer directly contacted with the semiconductor layer through the opening, 
   wherein a second region of the semiconductor layer does not overlap with the opening,   wherein the first region is thinner than the second region,   wherein the first channel formation region comprises silicon,   wherein the second channel formation region comprises an oxide semiconductor,   wherein a distance between a first edge of the second gate electrode and a first edge of the semiconductor layer is larger than a distance between a second edge of the second gate electrode and a second edge of the semiconductor layer,   wherein a part of the second gate electrode is positioned over the second channel formation region of the semiconductor layer, and   wherein a part of a bottom surface of the second gate electrode is positioned under a top surface of the semiconductor layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein a concentration of hydrogen in the second insulating layer below the third insulating layer is higher than a concentration of hydrogen in the fourth insulating layer over the third insulating layer. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein a transistor comprising the first channel formation region is a p-channel transistor. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein a transistor comprising the first channel formation region is an n-channel transistor. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the first metal layer penetrates the semiconductor layer. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the third gate electrode positions over the third insulating layer. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the first edge of the second gate electrode overlaps with the third gate electrode. 
     
     
         8 . A display device comprising the semiconductor device according to  claim 1 . 
     
     
         9 . A module comprising:
 the semiconductor device according to  claim 1 ;   an FPC; and   a frame.   
     
     
         10 . A electronic device comprising:
 the module according to  claim 9 ; and   at least one of a batter, a touch panel, and a backlight unit.   
     
     
         11 . A semiconductor device comprising a plurality of circuits arranged in an array:
 wherein each of the plurality of the circuits comprises:
 a first channel formation region; 
 a first insulating layer over the first channel formation region; 
 a first gate electrode over the first insulating layer, the first gate electrode overlapping with the first channel formation region; 
 a second insulating layer over the first gate electrode; 
 a third insulating layer over the second insulating layer, the third insulating layer is configured to block hydrogen; 
 a fourth insulating layer over the third insulating layer; 
 a second channel formation region over the fourth insulating layer, a semiconductor layer comprising the second channel formation region; 
 a fifth insulating layer over the second channel formation region; 
 a second gate electrode over the fifth insulating layer, the second gate electrode overlapping with the second channel formation region; 
 a third gate electrode directly connected to the second gate electrode, wherein the second gate electrode and the third gate electrode overlap with each other with the second channel formation region therebetween; and 
 a sixth insulating layer over the second gate electrode, the sixth insulating layer having an opening, wherein the opening overlaps with a first region of the semiconductor layer; 
 a first metal layer over the sixth insulating layer and in the opening, the first metal layer directly contacted with the semiconductor layer through the opening, 
   wherein a second region of the semiconductor layer does not overlap with the opening,   wherein the first region is thinner than the second region,   wherein the first channel formation region comprises single crystal silicon,   wherein the second channel formation region comprises an oxide semiconductor,   wherein a distance between a first edge of the second gate electrode and a first edge of the semiconductor layer is larger than a distance between a second edge of the second gate electrode and a second edge of the semiconductor layer,   wherein a part of the second gate electrode is positioned over the second channel formation region of the semiconductor layer, and   wherein a part of a bottom surface of the second gate electrode is positioned under a top surface of the semiconductor layer.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein a concentration of hydrogen in the second insulating layer below the third insulating layer is higher than a concentration of hydrogen in the fourth insulating layer over the third insulating layer. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein a transistor comprising the first channel formation region is a p-channel transistor. 
     
     
         14 . The semiconductor device according to  claim 11 , wherein a transistor comprising the first channel formation region is an n-channel transistor. 
     
     
         15 . The semiconductor device according to  claim 11 , wherein the first metal layer penetrates the semiconductor layer. 
     
     
         16 . The semiconductor device according to  claim 11 , wherein the third gate electrode positions over the third insulating layer. 
     
     
         17 . The semiconductor device according to  claim 11 , wherein the first edge of the second gate electrode overlaps with the third gate electrode. 
     
     
         18 . A display device comprising the semiconductor device according to  claim 11 . 
     
     
         19 . A module comprising:
 the semiconductor device according to  claim 11 ;   an FPC; and   a frame.   
     
     
         20 . A electronic device comprising:
 the module according to  claim 19 ; and   at least one of a batter, a touch panel, and a backlight unit.