Display device

Abstract

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

1 . (canceled) 
     
     
         2 . A display device comprising:
 a scan line driver circuit comprising:
 a second transistor; 
 a third transistor; 
 a fourth transistor; and 
 a fifth transistor, 
   wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,   wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,   wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,   wherein a gate of the second transistor is electrically connected to a fourth wiring,   wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,   wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,   wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,   wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the first transistor,   wherein a gate of the fourth transistor is electrically connected to a gate of the third transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring,   wherein a gate of the fifth transistor is electrically connected to a sixth wiring,   wherein the scan line driver circuit is configured to output an output signal to the first wiring,   wherein a first clock signal is supplied to the second wiring, and   wherein a second clock signal is supplied to the fourth wiring.   
     
     
         3 . The display device according to  claim 2 ,
 wherein the third wiring is a first power supply line.   
     
     
         4 . The display device according to  claim 2 ,
 wherein the fifth wiring is a second power supply line.   
     
     
         5 . The display device according to  claim 2 ,
 wherein the scan line driver circuit comprises a first stage and a second stage,   wherein the first stage comprises the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor, and   wherein a signal output from the second stage is input to the sixth wiring.   
     
     
         6 . A display device comprising:
 a scan line driver circuit comprising:
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; and 
 a seventh transistor, 
   wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,   wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,   wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,   wherein a gate of the second transistor is electrically connected to a fourth wiring,   wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,   wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,   wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,   wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the first transistor,   wherein a gate of the fourth transistor is electrically connected to a gate of the third transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring,   wherein a gate of the fifth transistor is electrically connected to a sixth wiring,   wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the third transistor,   wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,   wherein one of a source and a drain of the seventh transistor is electrically connected to the third wiring,   wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor,   wherein the scan line driver circuit is configured to output an output signal to the first wiring,   wherein a first clock signal is supplied to the second wiring, and   wherein a second clock signal is supplied to the fourth wiring.   
     
     
         7 . The display device according to  claim 6 ,
 wherein the third wiring is a first power supply line.   
     
     
         8 . The display device according to  claim 6 ,
 wherein the fifth wiring is a second power supply line.   
     
     
         9 . The display device according to  claim 6 ,
 wherein the scan line driver circuit comprises a first stage and a second stage,   wherein the first stage comprises the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor, and   wherein a signal output from the second stage is input to the sixth wiring.   
     
     
         10 . The display device according to  claim 9 ,
 wherein the scan line driver circuit further comprises a third stage,   wherein a gate of the seventh transistor is electrically connected to a seventh wiring, and   wherein a signal output from the third stage is input to the seventh wiring.   
     
     
         11 . The display device according to  claim 6 ,
 wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring.   
     
     
         12 . The display device according to  claim 6 ,
 wherein the scan line driver circuit further comprises an eighth transistor and a ninth transistor,   wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the third transistor,   wherein the other of the source and the drain of the eighth transistor is electrically connected to an eighth wiring,   wherein a gate of the eighth transistor is electrically connected to a ninth wiring,   wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the third transistor,   wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring,   wherein a gate of the ninth transistor is electrically connected to the fourth wiring,   wherein the eighth wiring is a third power supply line, and   wherein a third clock signal is supplied to the ninth wiring.