Enhanced directed system management interrupt mechanism

Abstract

An example compute node is disclosed that includes a plurality of processor cores. The example further includes an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state; and a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.

1 . (canceled) 
     
     
         2 . An apparatus comprising:
 instructions; and   at least one processor to execute the instructions to:
 trigger a first System Management Interrupt (SMI) for a core, the core in an idle state; 
 enter a system management mode (SMM) for the core to perform a plurality of operations corresponding to pending work based on the first SMI; 
 exit the SMM for the core based on an event, the core to delay performing a subset of the plurality operations not completed before the exit; 
 trigger a second SMI for the core based on completion of the event; and 
 enter the SMM for the core to perform the subset of the plurality of operations. 
   
     
     
         3 . The apparatus of  claim 2 , wherein the at least one processor is to provide control to a basic input output system (BIOS) based on the trigger of the first SMI for the core. 
     
     
         4 . The apparatus of  claim 2 , wherein the at least one processor is to provide control to an operating system (OS) based on the exit. 
     
     
         5 . The apparatus of  claim 2 , wherein the at least one processor is to determine when the core is to enter an idle state. 
     
     
         6 . The apparatus of  claim 5 , wherein the at least one processor is to invoke entry into the idle state for the core in response to determining the core is to enter the idle state. 
     
     
         7 . The apparatus of  claim 2 , wherein the at least one processor is to trigger the first SMI for the core based on the pending work. 
     
     
         8 . The apparatus of  claim 2 , wherein the at least one processor is to:
 detect an idle entry request at the core; and   trigger the first SMI for the core based on the idle entry request.   
     
     
         9 . The apparatus of  claim 8 , wherein the at least one processor is to detect the idle entry request at the core by determining a corresponding hardware assert for the first SMI indicates that the core is to run in the SMM. 
     
     
         10 . The apparatus of  claim 2 , wherein the event requires an operating system (OS) to be scheduled on the core to handle an interrupt or schedule a thread. 
     
     
         11 . The apparatus of  claim 10 , wherein the interrupt is a Translation Lookaside Buffer flush inter-processor interrupt, a scheduler dispatch interrupt, or a hardware interrupt. 
     
     
         12 . The apparatus of  claim 2 , wherein the at least one processor is to exit the SMM for the core within a predetermined time threshold. 
     
     
         13 . The apparatus of  claim 2 , wherein the plurality of operations includes platform management operations. 
     
     
         14 . One or more machine-readable storage devices comprising instructions, which when executed, cause one or more processors to at least:
 trigger a first System Management Interrupt (SMI) for a core, the core in an idle state;   enter a system management mode (SMM) for the core to perform a plurality of operations corresponding to pending work based on the first SMI;   exit the SMM for the core based on an event, the core to delay performing a subset of the plurality operations not completed before the exit;   trigger a second SMI for the core based on completion of the event; and   enter the SMM for the core to perform the subset of the plurality of operations.   
     
     
         15 . The one or more machine-readable storage devices of  claim 14 , wherein the instructions cause the one or more processors to provide control to a basic input output system (BIOS) based on the trigger of the first SMI for the core. 
     
     
         16 . The one or more machine-readable storage devices of  claim 14 , wherein the instructions cause the one or more processors to provide control to an operating system (OS) based on the exit. 
     
     
         17 . The one or more machine-readable storage devices of  claim 14 , wherein the instructions cause the one or more processors to:
 determine when the core is to enter an idle state; and   invoke entry into the idle state for the core in response to determining the core is to enter the idle state.   
     
     
         18 . The one or more machine-readable storage devices of  claim 14 , wherein the instructions cause the one or more processors to trigger the first SMI for the core based on the pending work. 
     
     
         19 . The one or more machine-readable storage devices of  claim 14 , wherein the instructions cause the one or more processors to:
 (a) determine that a corresponding hardware assert for the first SMI indicates that the core is to run in the SMM;   (b) detect an idle entry request at the core based (a); and   (c) trigger the first SMI for the core based on (b).   
     
     
         20 . The one or more machine-readable storage devices of  claim 14 , wherein the instructions cause the one or more processors to exit the SMM for the core within a predetermined time threshold. 
     
     
         21 . The one or more machine-readable storage devices of  claim 14 , wherein the plurality of operations include platform management operations.