Memory device interface and method

Abstract

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a substrate,   a host physical interface to memory, the host physical interface including connections for at least one memory channel, the connections for the memory channel including command/address (CA) connections, data connections (DQs), and ECC data/parity connections (ECC DQs);   multiple DRAM devices connected to form multiple sub-channels, each sub-channel including a respective portion of at least one DRAM device, wherein each DRAM portion is independently operable, and wherein each sub-channel includes one or more data paths, each data path coupled to a respective data DQ or ECC DQ;   wherein a bit width of each sub-channel, and independent operability of each DRAM portion, are configured to facilitate, via the host physical interface, error detection or correction, or both, of data in at least a single data path within a sub-channel.   
     
     
         2 . The apparatus of  claim 1 , wherein the memory channel is a DDR5-compatible memory channel, which includes 32 DQs and at least 4 ECC DQs; and wherein the multiple DRAM devices are connected to form at least nine sub-channels, of which memory cells of each sub-channel are independently addressable from memory cells of other sub-channels. 
     
     
         3 . The apparatus of  claim 2 , wherein the multiple DRAM devices are connected to form at least 18 sub-channels, of which each sub-channel is independently operable from each of the other sub-channels. 
     
     
         4 . The apparatus of  claim 3 , wherein the DRAM portions of the 18 sub-channels extend in at least 9 DRAM devices. 
     
     
         5 . The apparatus of  claim 2 , wherein the multiple DRAM devices are connected to form at least 20 sub-channels, of which each sub-channel is independently operable from each of the other sub-channels. 
     
     
         6 . The apparatus of  claim 5 , wherein the 20 sub-channels extend in at least 10 DRAM devices. 
     
     
         7 . The apparatus of  claim 5 , wherein the 20 sub-channels extend in at least 20 respective DRAM devices. 
     
     
         8 . The apparatus of  claim 3 , wherein each DRAM portion of the respective 18 sub-channels is associated with 2 data paths coupled to 2 DQs or 2 ECC DQs of the channel. 
     
     
         9 . The apparatus of  claim 8 , wherein memory cells of the respective DRAM portions are accessible by one or more local word lines which extend only within the respective DRAM portion, and which are driven by respective sub-word line drivers. 
     
     
         10 . The apparatus of  claim 9 , wherein the local word lines driven by respective sub-word line drivers within the respective DRAM portions serves to limit a number of DQs impacted by a failure of an individual sub-word line driver. 
     
     
         11 . The apparatus of  claim 9 , wherein each DRAM portion in a sub-channel includes a first number of array mats along a first direction in which a global word line extends, and a second number of array mats along a second direction perpendicular to the first direction, wherein the second number of array mats in the second direction is greater than the first number of array mats along the first direction. 
     
     
         12 . The apparatus of  claim 11 , wherein each array mat has respective addressable sub-word line drivers. 
     
     
         13 . The apparatus of  claim 12 , wherein control circuits controlling addressing and timing are separately provided for each array mat within a DRAM portion. 
     
     
         14 . The apparatus of  claim 11 , in which pairs of array mats share respective addressable sub-word line drivers. 
     
     
         15 . The apparatus of  claim 8 , wherein the DRAM portion of a sub-channel extends across multiple DRAM devices. 
     
     
         16 . The apparatus of  claim 2 , wherein the memory channel includes more than 4 ECC DQs. 
     
     
         17 . The apparatus of  claim 9 , where individual DRAM devices include internal ECC functionality to recover from local single or dual bit errors in a DRAM portion. 
     
     
         18 . A memory module, comprising:
 a substrate having a host physical interface, the host physical interface including connections for multiple memory channels, the connections for each memory channel including respective command/address (CA) connections, data connections (DQs), and ECC data/parity connections (ECC DQs);   
       multiple DRAM devices connected to form multiple sub-channels, each sub-channel including a respective DRAM portion in at least one DRAM device, wherein each sub-channel receives data from a subset of the data DQs and ECC DQs, wherein local word lines in each DRAM portion are independently addressable relative to local word lines in other DRAM portions;
 wherein the multiple memory channels are DDR5-compatible memory channels, which includes 32 DQs and more than 4 ECC DQs; and
 wherein the multiple DRAM devices are connected to form at least 18 sub-channels, and wherein each DRAM portion of the respective sub-channels is associated with up to 2 DQs or 2 ECC DQs of the memory channel; and 
 
 
       wherein recovery from a failed DRAM portion in a sub-channel can be performed under control of a host through the host interface, through use of the ECC DQs. 
     
     
         19 . The memory module of  claim 18 , where individual DRAM devices include internal ECC functionality to recover from local single or dual bit errors in a DRAM portion. 
     
     
         20 . The memory module of  claim 18 , wherein each DRAM portion in a sub-channel includes a first number of array mats along a first direction in which a global word line extends, and a second number of array mats along a second direction perpendicular to the first direction, wherein the second number of array mats in the second direction is greater than the first number of array mats along the first direction; and
 wherein each array mat has respective sub-word line drivers independently addressable from other array mats within the multiple sub-channels.