Unified addressing and hierarchical heterogeneous storage and memory

Abstract

According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

What is claimed is: 
     
         1 . An apparatus comprising:
 a processor configured to access a memory system;   a memory system comprising:
 a first storage medium associated with a first performance characteristic, and 
 a second storage medium associated with a second performance characteristic, and 
   a memory interconnect configured to route data between the processor and the first storage medium based, at least in part, on the first performance characteristic.   
     
     
         2 . The apparatus of  claim 1 , wherein the memory interconnect is configured to route data between the processor and the second storage medium based, at least in part, on the second performance characteristic. 
     
     
         3 . The apparatus of  claim 1 , wherein the processor is configured to use a unified access protocol to access the first storage medium and the second storage medium. 
     
     
         4 . The apparatus of  claim 3 , wherein the memory interconnect is configured to translate data between the unified access protocol and a medium specific protocol used by the first storage medium. 
     
     
         5 . The apparatus of  claim 1 , wherein:
 the first storage medium comprises volatile storage medium, and   the second storage medium comprises non-volatile storage medium.   
     
     
         6 . The apparatus of  claim 1 , wherein:
 the processor is configured to indicate a data category associated with the data, and   wherein the memory interconnect is configured to route the data to the first storage medium based, at least in part, on the data category.   
     
     
         7 . The apparatus of  claim 6 , wherein:
 the data category is based on compiling a software program, and   the processor is configured to access the data based, at least in part, on the software program.   
     
     
         8 . The apparatus of  claim 1 , wherein the memory interconnect is configured to organize the first storage medium and the second storage medium into a hierarchy based, at least in part, on the first performance characteristic and the second performance characteristic. 
     
     
         9 . The apparatus of  claim 8 , wherein the memory interconnect is configured to organize the hierarchy into a layered caching memory system. 
     
     
         10 . The apparatus of  claim 8 , wherein the memory interconnect is configured to organize the hierarchy based, at least in part, on a triggering event. 
     
     
         11 . A method comprising:
 receiving, from a processor, a data access for a memory system comprising:
 a first storage medium associated with a first performance characteristic, and 
 a second storage medium associated with a second performance characteristic, and 
   routing, by a memory interconnect, the data access, at least partially, between the processor and the first storage medium based, at least in part, on the first performance characteristic.   
     
     
         12 . The method of  claim 11 , wherein receiving the data access from the processor comprises receiving a first data access for the first storage medium via a first access protocol, the method further comprising receiving a second data access for the second storage medium via a second access protocol. 
     
     
         13 . The method of  claim 11 , further comprising organizing the first storage medium and the second storage medium into a hierarchy based, at least in part, on the first performance characteristic and the second performance characteristic. 
     
     
         14 . The method of  claim 13 , wherein:
 the organizing comprises organizing the first storage medium and the second storage medium into a layered caching memory system based, at least in part, on monitoring a first data access of the first storage medium and a second data access of the second storage medium, and   the routing is based, at least in part, on determining the first storage medium includes a piece of data associated with the data access.   
     
     
         15 . The method of  claim 13 , wherein the organizing comprises organizing the hierarchy into a layered caching memory system, the method further comprising mirroring a piece of data within a non-volatile layer of the layered caching memory system based, at least in part, on a layer of the layered caching memory system that includes the piece of data including a volatile storage medium. 
     
     
         16 . An apparatus comprising:
 a processor interface configured to receive a data access;   a first storage medium interface configured to communicate with a first storage medium of a memory system, the first storage medium interface being at least indirectly associated with a first performance characteristic of the first storage medium;   a second storage medium interface configured to communicate with a second storage medium of the memory system, the second storage medium interface being at least indirectly associated with a second performance characteristic of the second storage medium; and   a memory controller configured to route the data access between the processor interface and the first storage medium interface based, at least in part, on the first performance characteristic.   
     
     
         17 . The apparatus of  claim 16 , further comprising at least one accelerator processor configured to assist the memory controller route the data access between the processor interface and the first storage medium interface. 
     
     
         18 . The apparatus of  claim 17 , wherein the at least one accelerator processor comprises an encryption circuit configured to encrypt at least a data portion of the data access. 
     
     
         19 . The apparatus of  claim 17 , wherein the at least one accelerator processor comprises a protocol translation circuit configured to translate the data access from a first communications protocol to a second communication protocol. 
     
     
         20 . The apparatus of  claim 17 , wherein the at least one accelerator processor comprises a cache organizer circuit configured to:
 organize the memory system into a layered caching memory system,   maintain an inventory of the layered caching memory system, and   provide information regarding the layered caching memory system to the memory controller,   wherein the memory controller is configured to select the first storage medium interface based, at least in part, on the information regarding the layered caching memory system.