High electron mobility transistor and method of manufacturing the same

Abstract

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

What is claimed is: 
     
         1 . A high electron mobility transistor comprising:
 a channel layer including a first semiconductor material;   a channel supplying layer including a second semiconductor material and causing generation of a two-dimensional electron gas (2DEG) in the channel layer;   a source electrode and a drain electrode provided on both sides of the channel supplying layer;   a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG;   a gate electrode provided on a portion of the depletion forming layer; and   a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer, and configured to limit a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.   
     
     
         2 . The high electron mobility transistor of  claim 1 , wherein
 the depletion forming layer comprises a p-type III-V group nitride semiconductor, and   the current limiting layer comprises an n-type III-V group nitride semiconductor.   
     
     
         3 . The high electron mobility transistor of  claim 1 , wherein the gate electrode comprises an upper portion in contact with an upper surface of the current limiting layer and a lower portion in contact with a side surface of the current limiting layer. 
     
     
         4 . The high electron mobility transistor of  claim 3 , wherein the depletion forming layer is of an integral type and extends in a direction parallel to the gate electrode. 
     
     
         5 . The high electron mobility transistor of  claim 4 , wherein the current limiting layer is respectively provided on both sides of a lower side of the gate electrode. 
     
     
         6 . The high electron mobility transistor of  claim 5 , wherein the current limiting layer is of an integral type and extends in a direction parallel to the gate electrode. 
     
     
         7 . The high electron mobility transistor of  claim 5 , wherein the current limiting layer includes portions spaced apart from each other in a direction parallel to the gate electrode. 
     
     
         8 . The high electron mobility transistor of  claim 4 , wherein the current limiting layer surrounds a lower portion of the gate electrode. 
     
     
         9 . The high electron mobility transistor of  claim 3 , wherein the depletion forming layer has portions spaced apart from each other in a direction parallel to the gate electrode. 
     
     
         10 . The high electron mobility transistor of  claim 9 , wherein the current limiting layer is respectively provided on both sides of a lower side of the gate electrode. 
     
     
         11 . The high electron mobility transistor of  claim 10 , wherein the current limiting layer is of an integral type and extends in a direction parallel to the gate electrode. 
     
     
         12 . The high electron mobility transistor of  claim 10 , wherein the current limiting layer includes portions spaced apart from each other in a direction parallel to the gate electrode. 
     
     
         13 . The high electron mobility transistor of  claim 9 , wherein the current limiting layer surrounds a lower portion of the gate electrode. 
     
     
         14 . The high electron mobility transistor of  claim 3 , further comprising:
 an etch stop layer between the gate electrode and the current limiting layer and the depletion forming layer.   
     
     
         15 . The high electron mobility transistor of  claim 1 , wherein the first semiconductor material comprises a GaN-based material. 
     
     
         16 . The high electron mobility transistor of  claim 1 , wherein the second semiconductor material comprises a nitride including at least one of Al, Ga, In, and B. 
     
     
         17 . A method of manufacturing a high electron mobility transistor, the method comprising:
 forming a channel layer and a channel supplying layer;   forming a depletion forming layer on the channel supplying layer;   forming a current limiting layer on the depletion forming layer;   patterning the current limiting layer to form a trench that exposes the depletion forming layer; and   forming a gate electrode in the current limiting layer to fill the trench.   
     
     
         18 . The method of  claim 17 , further comprising:
 after forming the depletion forming layer, forming an etch stop layer on the depletion forming layer.   
     
     
         19 . The method of  claim 17 , wherein the current limiting layer is respectively formed on both sides of a lower side of the gate electrode. 
     
     
         20 . The method of  claim 17 , wherein the current limiting layer is formed to surround a lower portion of the gate electrode.