Method and device for digital compensation of dynamic distortion in high-speed transmitters
Abstract
A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of operating a transmitter device, the method comprising:
providing a lookup table (LUT) with a plurality of starting values; and iteratively performing, until one or more check conditions are met, the following: sending an input signal pattern through the LUT to a digital-to-analog converter (DAC) to produce an output waveform; capturing the output waveform using a recording device; determining a desired output value using the captured output waveform for each possible sequence of three input symbols; and determining and storing, in the LUT, an estimated LUT value for each possible sequence of three input symbols associated with the desired output value corresponding to the same sequence of three input symbols; wherein the transmitter includes a first shift register configured with the LUT to produce a first delayed input signal pattern and a second shift register configured with the LUT to produce a second delayed input signal pattern; and wherein the input signal pattern, the first delayed input signal pattern, and the second delayed input signal pattern are used to provide each possible sequence of three input symbols used to determine the desired output values and the estimated LUT values.
2 . The method of claim 1 wherein determining the desired output value includes determining an average output value using the captured output waveform for each possible sequence of three input symbols and determining the desired output value using the average output value for each possible sequence of three input symbols.
3 . The method of claim 1 wherein determining the desired output values and determining the estimated LUT values are performed by a digital signal processor (DSP); and
wherein storing the estimated LUT values in the LUT comprises communicating, by the DSP, the estimated LUT values over a back channel configured between the transmitter device and the recording device.
4 . The method of claim 1 wherein determining the desired output values includes applying linear equalization, eye modulation, or amplitude scaling for each sequence of three input symbols; and
wherein determining the estimated LUT values includes applying a least mean squared (LMS) algorithm, a recursive least squares (RLS) algorithm, or an Affine Projection (AP) algorithm.
5 . The method of claim 1 further comprising, iteratively performing, the step of adjusting the desired output values, including
determining a sequence of three input symbols that is most likely to clip at an upper end of the output waveform;
determining a sequence of three input symbols that is most likely to clip at a lower end of the output waveform; and
shifting and scaling the desired output values according to the sequences most likely to clip at the upper and lower ends.
6 . The method of claim 1 wherein the one or more check conditions includes a target signal to noise and distortion ratio (SNDR), eye height, bit error rate (BER), level separation mismatch ratio (RLM), or transmission dispersion and eye closure quaternary (TDECQ).
7 . A transmitter device, the device comprising:
a lookup table (LUT) having a plurality of LUT entries configured to receive an input signal, the LUT being configured to output an LUT output signal according to the plurality of LUT entries; a first shift register coupled to the LUT and configured to provide a first delayed input signal to the LUT; a second shift register coupled to the LUT and configured to provide a second delayed input signal to the LUT; a digital-to-analog converter (DAC) coupled to the LUT and configured to receive the LUT output signal and to output a DAC output signal; a recording device coupled to the DAC and configured to capture the DAC output signal; and a digital signal processor (DSP) coupled to the LUT, the DAC, and the recording device; wherein the DSP is configured to provide the LUT with a plurality of starting values in the plurality of LUT entries; and configured to iteratively perform, until one or more check conditions are met, the following: sending an input signal pattern as the input signal through the LUT to a digital-to-analog converter (DAC) to produce an output waveform in the DAC output signal; capturing the output waveform from the DAC output signal using the recording device; determining a desired output value using the captured output waveform for each possible sequence of three input symbols; and determining and storing, in the plurality of LUT entries, an estimated LUT value for each possible sequence of three input symbols associated with the desired output value corresponding to the same sequence of three input symbols;
wherein the input signal, the first delayed input signal, and the second delayed input signal are used to provide each possible sequence of three input symbols used to determine the desired output values and the estimated LUT values.
8 . The device of claim 7 wherein the recording device includes an on-chip receiver or a digital scope.
9 . The device of claim 7 wherein the DSP is configured to determine the desired output value by determining an average output value using the captured output waveform for each possible sequence of three input symbols and determining the desired output value using the average output value for each possible sequence of three input symbols.
10 . The device of claim 7 wherein the DSP is configured to determine the desired output values by applying linear equalization, eye modulation, or amplitude scaling for each sequence of three input symbols.
11 . The device of claim 7 wherein the DSP is configured to iteratively perform, the step of adjusting the desired output values by
determining a sequence of three input symbols that is most likely to clip at an upper end of the output waveform;
determining a sequence of three input symbols that is most likely to clip at a lower end of the output waveform; and
shifting and scaling the desired output values according to the sequences most likely to clip at the upper and lower ends.
12 . The device of claim 7 wherein the DSP is configured to determine the estimated LUT values by applying a least mean squared (LMS) algorithm, a recursive least squares (RLS) algorithm, or an Affine Projection (AP) algorithm.
13 . The device of claim 7 wherein the one or more check conditions includes a target signal to noise and distortion ratio (SNDR), eye height, bit error rate (BER), level separation mismatch ratio (RLM), or transmission dispersion and eye closure quaternary (TDECQ).
14 . A communication system, the system comprising:
a receiver device; a communication channel coupled to the receiver device; and a transmitter device coupled to the communication channel, the transmitter device comprising:
a lookup table (LUT) having a plurality of LUT entries configured to receive an input signal from the receiver device over the communication channel, the LUT being configured to output an LUT output signal according to the plurality of LUT entries;
a first shift register coupled to the LUT and configured to provide a first delayed input signal to the LUT;
a second shift register coupled to the LUT and configured to provide a second delayed input signal to the LUT;
a digital-to-analog converter (DAC) coupled to the LUT and configured to receive the LUT output signal and to output a DAC output signal;
a recording device coupled to the DAC and configured to capture the DAC output signal; and
a digital signal processor (DSP) coupled to the LUT, the DAC, and the recording device; wherein the DSP is configured to provide the LUT with a plurality of starting values in the plurality of LUT entries; and configured to iteratively perform, until one or more check conditions are met, the following:
sending an input signal pattern as the input signal through the LUT to a digital-to-analog converter (DAC) to produce an output waveform in the DAC output signal;
capturing the output waveform from the DAC output signal using the recording device;
determining a desired output value using the captured output waveform for each possible sequence of three input symbols; and
determining and storing, in the plurality of LUT entries, an estimated LUT value for each possible sequence of three input symbols associated with the desired output value corresponding to the same sequence of three input symbols;
wherein the input signal, the first delayed input signal, and the second delayed input signal are used to provide each possible sequence of three input symbols used to determine the desired output values and the estimated LUT values.
15 . The system of claim 14 wherein the recording device includes an on-chip receiver or a digital scope.
16 . The system of claim 14 wherein the DSP is configured to determine the desired output value by determining an average output value using the captured output waveform for each possible sequence of three input symbols and determining the desired output value using the average output value for each possible sequence of three input symbols.
17 . The system of claim 14 wherein the DSP is configured to determine the desired output values by applying linear equalization, eye modulation, or amplitude scaling for each sequence of three input symbols.
18 . The system of claim 14 wherein the DSP is configured to iteratively perform, the step of adjusting the desired output values by
determining a sequence of three input symbols that is most likely to clip at an upper end of the output waveform;
determining a sequence of three input symbols that is most likely to clip at a lower end of the output waveform; and
shifting and scaling the desired output values according to the sequences most likely to clip at the upper and lower ends.
19 . The system of claim 14 wherein the DSP is configured to determine the estimated LUT values by applying a least mean squared (LMS) algorithm, a recursive least squares (RLS) algorithm, or an Affine Projection (AP) algorithm.
20 . The system of claim 14 wherein the one or more check conditions includes a target signal to noise and distortion ratio (SNDR), eye height, bit error rate (BER), level separation mismatch ratio (RLM), or transmission dispersion and eye closure quaternary (TDECQ).Join the waitlist — get patent alerts
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