Dielectric barrier at non-volatile memory tile edge

Abstract

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

What is claimed is: 
     
         1 . A non-volatile memory device comprising:
 multiple tiers of memory tiles, the multiple tiers vertically stacked over one another, each of the memory tiles including a plurality of memory cells, each of the plurality of memory cells including a layer of chalcogenide material between a first conductive access line and a second conductive access line; and   an oxidation barrier on a side wall of a trench between adjacent memory tiles, wherein the trench between the adjacent memory tiles includes tapered side walls.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier comprises a silicon nitride film.   
     
     
         3 . The non-volatile memory device of  claim 2 , wherein:
 the silicon nitride film has a density that is greater than 2.6 g/cm3.   
     
     
         4 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier has a thickness in a range between 15-500 Angstroms.   
     
     
         5 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier comprises multiple nitride films.   
     
     
         6 . The non-volatile memory device of  claim 5 , wherein:
 the multiple nitride films include:
 a first nitride film and one or more second nitride films over the first nitride film, wherein the first nitride film is thicker than the one or more second nitride films. 
   
     
     
         7 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier comprises a conformal layer over the tapered side walls of the trench.   
     
     
         8 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier is further disposed on a bottom of the trench.   
     
     
         9 . The non-volatile memory device of  claim 1 , wherein:
 the trench comprises a wide trench that is wider than it is deep.   
     
     
         10 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier is on a chalcogenide material exposed at the side wall of the trench.   
     
     
         11 . The non-volatile memory device of  claim 1 , wherein:
 the oxidation barrier is on a carbon layer exposed at the side wall of the trench.   
     
     
         12 . A non-volatile memory device comprising:
 multiple tiers of memory tiles, the multiple tiers vertically stacked over one another, each of the memory tiles including a plurality of memory cells;   a trench through the multiple tiers between a pair of adjacent memory tiles, wherein the trench between the pair of adjacent memory tiles includes tapered side walls; and   a silicon nitride film on a side wall of the trench between adjacent memory tiles.   
     
     
         13 . The non-volatile memory device of  claim 12 , wherein:
 the silicon nitride film has a density that is greater than 2.6 g/cm3.   
     
     
         14 . The non-volatile memory device of  claim 12 , wherein:
 the silicon nitride film has a thickness in a range between 15-500 Angstroms.   
     
     
         15 . The non-volatile memory device of  claim 12 , further comprising:
 one or more second nitride films over the silicon nitride film.   
     
     
         16 . The non-volatile memory device of  claim 15 , wherein:
 the silicon nitride film is thicker than the one or more second nitride films.   
     
     
         17 . The non-volatile memory device of  claim 12 , wherein:
 the silicon nitride film comprises a conformal layer over the tapered side walls of the trench.   
     
     
         18 . The non-volatile memory device of  claim 12 , wherein:
 the silicon nitride film is further disposed on a bottom of the trench.   
     
     
         19 . The non-volatile memory device of  claim 12 , wherein:
 the trench comprises a wide trench that is wider than it is deep.   
     
     
         20 . The non-volatile memory device of  claim 12 , wherein:
 the silicon nitride film is on a chalcogenide material exposed at the side wall of the trench.   
     
     
         21 . A system comprising:
 a processor; and   a non-volatile memory device coupled with the processor, the non-volatile memory device including:
 multiple tiers of memory tiles, the multiple tiers vertically stacked over one another, each of the memory tiles including a plurality of memory cells, each of the plurality of memory cells including a layer of chalcogenide material between a first conductive access line and a second conductive access line; and 
 an oxidation barrier on a side wall of a trench between adjacent memory tiles, wherein the trench between the adjacent memory tiles includes tapered side walls. 
   
     
     
         22 . The system of  claim 21 , wherein:
 the non-volatile memory device is included in a dual inline memory module (DIMM) or a solid state drive (SSD).