Logic circuit and semiconductor device

Abstract

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a logic circuit in which a first signal, a second signal, and a clock signal are input,   wherein the logic circuit is configured to output a first output signal and a second output signal,   wherein the logic circuit comprises a plurality of transistors,   wherein each of the plurality of transistors comprises a crystallized oxide semiconductor layer having indium, gallium, and zinc, and   wherein an off-current per 1 μm of a channel width of each of the plurality of transistors is less than or equal to 1×10 −17  A at a source-drain voltage of 10V and a source-gate voltage range of −2V to 20V.   
     
     
         3 . A semiconductor device comprising:
 a logic circuit in which a first signal, a second signal, and a clock signal are input,   wherein the logic circuit is configured to output a first output signal and a second output signal,   wherein the logic circuit comprises a plurality of transistors,   wherein each of the plurality of transistors comprises a microcrystalline oxide semiconductor layer having indium, gallium, and zinc, and   wherein an off-current per 1 μm of a channel width of each of the plurality of transistors is less than or equal to 1×10 −17  A at a source-drain voltage of 10V and a source-gate voltage range of −2V to 20V.