Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices

Abstract

A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

1 . (canceled) 
     
     
         2 . A 3D NAND Flash memory chip comprising:
 a plurality of p-wells isolated from each other, the plurality of p-wells comprising a first p-well and a second p-well;   a plurality of n+ source line regions, each n+ source line region being disposed at one of the plurality of p-wells;   a first plurality of pillars disposed on the first p-well and a second plurality of pillars disposed on the second p-well,
 each of the first plurality of pillars extending in a vertical direction from the first p-well and each of the second plurality of pillars extending in the vertical direction from the second p-well, and 
 each pillar of the first plurality of pillars and the second plurality of pillars containing a pillar body, a string select transistor, a sourceline select transistor, and a plurality of n-channel memory cell transistors, each string select transistor, each sourceline select transistor and each n-channel memory cell transistor comprising a gate wrapping around the pillar body to form a gate-all-around structure, and 
 the gate of each string select transistor coupled to a corresponding string select line, the gate of each sourceline select transistor couple to a corresponding ground select line and the gate of each n-channel memory cell transistor coupled to a corresponding word line, and 
 the plurality of n-channel memory cell transistors in each pillar vertically stacked to form a three dimensional vertical channel NAND string structure, 
 wherein the pillar body of each pillar of the first plurality of pillars and each pillar of the second plurality of pillars extends from a location of its corresponding p-well between two neighboring n+ source line regions, the two neighboring n+ source line regions being separated from the pillar body in alignment with outer edges of the corresponding ground select line; and 
 a first p+ contact region formed on the first p-well and a second p+ contact region formed on the second p-well. 
   
     
     
         3 . The 3D NAND Flash memory chip of  claim 2  further comprising an n-type diffused region disposed at a top end of each pillar of the first plurality of pillars and each pillar of the second plurality of pillars. 
     
     
         4 . The 3D NAND Flash memory chip of  claim 3  further comprising a plurality of bit lines, wherein each n-type diffused region disposed at the top of a pillar contacts one of the plurality of bit lines. 
     
     
         5 . The 3D NAND Flash memory chip of  claim 2 , wherein the first p-well and the second p-well are arranged proximate to each other in a bit line direction. 
     
     
         6 . The 3D NAND Flash memory chip of  claim 2  further comprising a plurality of bit lines, wherein at least one bit line of the plurality of bit lines is connected to a pillar of the first plurality of pillars and to a pillar of the second plurality of pillars. 
     
     
         7 . The 3D NAND Flash memory chip of  claim 2 , wherein the first p+ contact region is connected to a first local erase line and the second p+ contact region is connected to a second local erase line. 
     
     
         8 . The 3D NAND Flash memory chip of  claim 7 , wherein the first local erase line is connected to a first erase voltage pass transistor and the second local erase line is connected to a second erase voltage pass transistor. 
     
     
         9 . The 3D NAND Flash memory chip of  claim 8 , further comprising:
 a first pass block circuit comprising the first erase voltage pass transistor; and   a second pass block circuit comprising the second erase voltage pass transistor.   
     
     
         10 . The 3D NAND Flash memory chip of  claim 7 , wherein the first local erase line and the second local erase line are connected to a common local erase line.