US2021288124A1PendingUtilityA1

Display panel, display device, input/output device, and data processing device

Assignee: SEMICONDUCTOR ENERGY LABPriority: Dec 27, 2016Filed: May 28, 2021Published: Sep 16, 2021
Est. expiryDec 27, 2036(~10.4 yrs left)· nominal 20-yr term from priority
H10K 59/1213G09G 3/3233H10D 86/441H10D 86/0212H10D 30/6755H10D 30/6704H10D 99/00H10D 89/601H10D 86/481H10D 86/423H10D 86/60G09G 2310/027G06F 3/0412G06F 2203/04103G09G 2330/04G09G 2330/06G09G 3/2007G06F 2203/04101G09G 2354/00H01L 27/3276H01L 27/0251H01L 27/1255H01L 51/56H01L 29/66969H01L 29/7869H01L 27/3218H01L 27/1225H01L 27/3248H01L 27/3258H01L 27/3265H01L 27/3262H01L 2227/323H01L 27/124H10K 59/131H10K 59/1201H10K 59/124H10K 59/353H10K 59/1216H10K 59/123H10K 71/00H10K 71/166H10K 71/60
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Claims

Abstract

A novel display panel that is highly convenient or reliable is provided. The display panel includes a display region, and the display region includes a first group of pixels, a second group of pixels, a third group of pixels, a fourth group of pixels, a first scan line, a second scan line, a first signal line, and a second signal line. The first group of pixels include a first pixel and are arranged in a row direction. The second group of pixels include a second pixel and are arranged in the row direction. The third group of pixels include a first pixel and are arranged in a column direction that intersects the row direction. The fourth group of pixels include a second pixel and are arranged in the column direction. The first signal line is electrically connected to the third group of pixels and the second signal line is electrically connected to the fourth group of pixels. The first scan line is electrically connected to the first group of pixels and the second scan line is electrically connected to the second group of pixels.

Claims

exact text as granted — not AI-modified
1 . A display panel comprising:
 a pixel that comprises a functional layer and a display element,   wherein the functional layer comprises a transistor, electrically connected to the display element, in a light-transmitting region transmitting visible light, and   wherein the light-transmitting region has a transmittance to red, green, and blue light of 60% or more.   
     
     
         2 . The display panel according to  claim 1 ,
 wherein the transistor is positioned closer to a user that the display element.   
     
     
         3 . The display panel according to  claim 1 ,
 wherein the functional layer comprises a capacitor in the light-transmitting region.   
     
     
         4 . The display panel according to  claim 1 ,
 wherein the functional layer comprises a first insulating film and a second insulating film,   wherein the first insulating film has a region sandwiched between the transistor and the display element and a first opening portion,   wherein the second insulating film has a region sandwiched between the transistor and the first insulating film and a second opening portion,   whereon the second opening portion has a region overlapping with the first opening portion and has an outer edge aligned with that of the first opening portion, and   wherein the display element is electrically connected to the transistor through the first opening portion and the second opening portion.   
     
     
         5 . The display panel according to  claim 1 ,
 wherein the transistor is a dual-gate transistor,   wherein a top-gate of the transistor is electrically connected to a first electrode of a capacitor and one of a source and a drain of a second transistor,   wherein one of a source and a drain of the transistor is electrically connected to a first wiring, a part of the first wiring functioning as a second electrode of the capacitor.   
     
     
         6 . The display panel according to  claim 1 ,
 wherein a first wiring is provided between a second wiring and a third wiring, each of the second wiring and the third wring functioning as a source line,   wherein the first wiring is provided between the transistor and a second transistor, and   wherein the transistor and the second transistor are provided between the second wiring and the third wiring.   
     
     
         7 . The display panel according to  claim 6 ,
 wherein a gate line intersects with the first wiring, the second wiring and the third wiring, and   wherein the first wiring is narrower in a region in which an opening is formed in the first wiring.   
     
     
         8 . The display panel according to  claim 6 ,
 wherein the pixel has an aperture ratio of higher than or equal to 20%.   
     
     
         9 . The display panel according to  claim 6 ,
 wherein the display panel applies a white tandem OLED.

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