Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects

Abstract

An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a package substrate;   a first configurable integrated circuit (IC), mounted on the package substrate, comprising a first programmable fabric, k*n number of first wires coupled to the first programmable fabric and extending from the first programmable fabric, n first time division multiplexers (TDMs), and n first IO blocks, wherein each of the first TDMs comprises k inputs that are coupled to k of the first wires and an output coupled to one of the first IO blocks; and   a second configurable IC, mounted on the package substrate, comprising a second programmable fabric, k*n second wires coupled to the second programmable fabric and extending from the second programmable fabric, n second TDMs hardwired outside of the second programmable fabric, and n second IO blocks, wherein each of the second TDMs comprises k inputs that are coupled to k of the second wires and an output coupled to one of the second IO blocks, and the first and second IO blocks are coupled in a one-to-one manner via the package substrate.   
     
     
         2 . The semiconductor device of  claim 1  wherein the first TDMs are not formed in the first programmable fabric and the second TDMs are not formed in the second programmable fabric. 
     
     
         3 . The semiconductor device of  claim 1  wherein each of the first wires is coupled to one of the first TDMs and is not coupled to a second one of the first TDMs, and each of the second wires is coupled to one of the second TDMs and is not coupled to a second one of the second TDMs. 
     
     
         4 . The semiconductor device of  claim 1  wherein the package substrate comprises an interconnect bridge and the first and second IO blocks are coupled in a one-to-one manner via the interconnect bridge. 
     
     
         5 . The semiconductor device of  claim 4  wherein the first configurable IC comprises n first IO elements and each of the first IO blocks is coupled to one of the first IO elements, the second configurable IC comprises n second IO elements and each of the second IO blocks is coupled to one of the second IO elements, and the interconnect bridge couples the first and second IO elements in a one-to-one manner. 
     
     
         6 . The semiconductor device of  claim 1  wherein the first TDMs are hardwired outside of the first programmable fabric. 
     
     
         7 . A semiconductor device comprising:
 a package substrate;   a first integrated circuit (IC), mounted on the package substrate, comprising a first programmable fabric, k*n number of first wires coupled to the first programmable fabric and extending from the first programmable fabric, an n number of first time division multiplexers (TDMs), and an n number of first IO blocks, wherein each of the first TDMs comprises a k number of inputs that are coupled to a k number of the first wires and an output coupled to one of the first IO blocks; and   a second IC, mounted on the package substrate, comprising a second programmable fabric, k*n second wires coupled to the second programmable fabric and extending from the second programmable fabric, an n number of second TDMs, and an n number of second IO blocks, wherein each of the second TDMs comprises a k number of inputs that are coupled to a k number of the second wires and an output coupled to one of the second IO blocks.   
     
     
         8 . The semiconductor device of  claim 7  wherein the first and second IO blocks are coupled in a one-to-one manner via the package substrate. 
     
     
         9 . The semiconductor device of  claim 7  wherein the first TDMs are hardwired outside of the first programmable fabric, and wherein second TDMs are hardwired outside of the second programmable fabric. 
     
     
         10 . The semiconductor device of  claim 7  wherein the first TDMs are not formed in the first programmable fabric and the second TDMs are not formed in the second programmable fabric. 
     
     
         11 . The semiconductor device of  claim 7  wherein each of the first wires is coupled to one of the first TDMs and is not coupled to a second one of the first TDMs, and each of the second wires is coupled to one of the second TDMs and is not coupled to a second one of the second TDMs. 
     
     
         12 . The semiconductor device of  claim 7  wherein the package substrate comprises an interconnect bridge and the first and second IO blocks are coupled in a one-to-one manner via the interconnect bridge. 
     
     
         13 . The semiconductor device of  claim 12  wherein the first IC comprises an n number of first IO elements and each of the first IO blocks is coupled to one of the first IO elements, the second IC comprises an n number of second IO elements and each of the second IO blocks is coupled to one of the second IO elements, and the interconnect bridge couples the first and second IO elements in a one-to-one manner. 
     
     
         14 . A method for manufacturing a semiconductor device, the method comprising:
 providing a package substrate;   mounting a first integrated circuit (IC) on the package substrate, wherein the first IC comprises a first programmable fabric, k*n number of first wires coupled to the first programmable fabric and extending from the first programmable fabric, an n number of first time division multiplexers (TDMs), and an n number of first IO blocks, wherein each of the first TDMs comprises a k number of inputs that are coupled to a k number of the first wires and an output coupled to one of the first IO blocks; and   mounting a second IC on the package substrate, wherein the second IC comprises a second programmable fabric, k*n second wires coupled to the second programmable fabric and extending from the second programmable fabric, an n number of second TDMs, and an n number of second IO blocks, wherein each of the second TDMs comprises a k number of inputs that are coupled to a k number of the second wires and an output coupled to one of the second IO blocks.   
     
     
         15 . The method of  claim 14  wherein the first and second IO blocks are coupled in a one-to-one manner via the package substrate. 
     
     
         16 . The method of  claim 14  wherein the first TDMs are not formed in the first programmable fabric and the second TDMs are not formed in the second programmable fabric. 
     
     
         17 . The method of  claim 14  wherein each of the first wires is coupled to one of the first TDMs and is not coupled to a second one of the first TDMs, and each of the second wires is coupled to one of the second TDMs and is not coupled to a second one of the second TDMs. 
     
     
         18 . The method of  claim 14  wherein the package substrate comprises an interconnect bridge and the first and second IO blocks are coupled in a one-to-one manner via the interconnect bridge. 
     
     
         19 . The method of  claim 18  wherein the first IC comprises an n number of first IO elements and each of the first IO blocks is coupled to one of the first IO elements, the second IC comprises an n number of second IO elements and each of the second IO blocks is coupled to one of the second IO elements, and the interconnect bridge couples the first and second IO elements in a one-to-one manner. 
     
     
         20 . The method of  claim 14  wherein the first TDMs are hardwired outside of the first programmable fabric, and wherein second TDMs are hardwired outside of the second programmable fabric.