Semiconductor device and method of fabricating the same

Abstract

A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

1 . A method of fabricating a semiconductor device, comprising:
 forming a plurality of first vias in a first dielectric layer in a memory cell region and a peripheral region;   performing a surface treatment on the plurality of first vias, so as to form a plurality of sacrificial layers;   removing the plurality of sacrificial layers so as to form a plurality of recesses;   forming a plurality of protective layers in the plurality of recesses;   forming a memory device on the first dielectric layer in the memory cell region;   forming a second dielectric layer on the memory device and the first dielectric layer; and   forming a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region, so as to electrically connect to the memory device in the memory cell region and the first vias in the peripheral region, respectively.   
     
     
         2 . The method according to  claim 1 , wherein the forming the memory device comprises:
 forming a first electrode, a variable resistance layer, a second electrode and a capping layer on the first dielectric layer and the plurality of protective layers; and   patterning the capping layer, the second electrode, the variable resistance layer, and the first electrode to form the memory device in contact with the plurality of protective layers.   
     
     
         3 . The method according to  claim 1 , wherein the forming the memory device comprises:
 serving the plurality of protective layers as the first electrodes;   forming a variable resistance layer, a second electrode and a capping layer on the plurality of protective layers; and   patterning the second electrode, the variable resistance layer, and the first electrode to form the memory device in contact with the first vias.   
     
     
         4 . The method according to  claim 1 , further comprising removing the plurality of protective layers in the peripheral region before the forming the second vias, wherein the second vias in the peripheral region are in physical contact with the first vias. 
     
     
         5 . The method according to  claim 1 , wherein the second vias and the first vias in the peripheral region are electrically connected through the plurality of protective layers. 
     
     
         6 . A semiconductor device, comprising:
 a plurality of first vias in a first dielectric layer in a memory cell region and a peripheral region respectively;   a plurality of protective layers embedded in the plurality of first vias;   a memory device located on the plurality of protective layers and the first dielectric layer in the memory cell region;   a second dielectric layer on the memory device and the first dielectric layer; and   a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region, wherein the second vias in the memory cell region are electrically connected to the memory device, and the second vias in the peripheral region are electrically connected to the first vias through the plurality of protective layers.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the plurality of protective layers and the plurality of first vias comprise different conductive materials. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein one of the plurality of protective layers serve as a first electrodes of the memory device. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein the plurality of protective layers have a thickness less than a thickness of a second electrode of the memory device. 
     
     
         10 . The semiconductor device according to  claim 6 , wherein the plurality of protective layers are in contact with the first electrode of the memory device. 
     
     
         11 . The semiconductor device according to  claim 6 , wherein the plurality of protective layers have a thickness less than a thickness of a second electrode of the memory device.