Crack suppression structure for hv isolation component

Abstract

An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.

1 . An integrated circuit (IC), comprising:
 a substrate having functional circuitry for realizing at least one circuit function with at least one high voltage isolation component including a top metal feature above the substrate;   a crack suppressing dielectric structure comprising at least a dielectric layer on a top surface of the top metal feature, and a dielectric passivation overcoat (PO) layer that touches a top surface of the crack suppressing dielectric structure and a side surface of the top metal feature.   
     
     
         2 . The IC of  claim 1 , wherein the crack suppressing dielectric structure also touches a side surface of the crack suppressing dielectric structure. 
     
     
         3 . The IC of  claim 1 , wherein the crack resistant dielectric layer comprises silicon nitride (SiN) layer or a silicon carbide (SiC) layer. 
     
     
         4 . The IC of  claim 3 , wherein the SiN layer or the SiC layer has a thickness in a range between 20 nm and 80 nm and has a compressive stress in a range between 50 MPa and 500 MPa. 
     
     
         5 . The IC of  claim 1 , wherein the crack suppressing dielectric layer comprises a silicon nitride (SiN) layer that is between a top silicon oxide layer and a bottom silicon oxide layer. 
     
     
         6 . The IC of  claim 1 , wherein the high voltage isolation component comprises a capacitor. 
     
     
         7 . The IC of  claim 1 , wherein the high voltage isolation component comprises a transformer, and wherein the top metal feature comprises a top electrode inductively coupled to an outer positioned inductance coil. 
     
     
         8 . An integrated circuit (IC), comprising:
 a substrate having functional circuitry for realizing at least one circuit function with at least one high voltage isolation component including a top metal feature above the substrate;   a first metal interconnect level, at least one second metal interconnect level over the first metal interconnect level, and a third metal interconnect level over the at least one second metal interconnect level, the third metal interconnect level including the top metal feature;   a crack suppressing dielectric structure comprising at least one crack resistant dielectric layer on the top metal feature;   a dielectric passivation overcoat (PO) layer over the top metal feature.   
     
     
         9 . The IC of  claim 8 , wherein the crack suppressing dielectric structure has sidewalls that extend from sidewall of the top metal feature. 
     
     
         10 . The IC of  claim 8 , wherein the crack suppressing dielectric structure covers sidewalls of the top metal feature. 
     
     
         11 . The IC of  claim 8 , wherein the crack resistant dielectric layer comprises a silicon nitride (SiN) layer or a silicon carbide (SiC) layer. 
     
     
         12 . The IC of  claim 11 , wherein the SiN layer or the SiC layer has a thickness in a range between 20 nm and 80 nm and has a compressive stress in a range between 50 MPa and 500 MPa. 
     
     
         13 . The IC of  claim 8 , wherein the crack resistant dielectric layer comprises a plasma enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) layer. 
     
     
         14 . The IC of  claim 13 , wherein the crack suppressing dielectric structure further comprises a SiN layer between and touching a bottom silicon oxide layer and a top silicon oxide layer. 
     
     
         15 . The IC of  claim 8 , wherein the dielectric PO layer has a planar top surface. 
     
     
         16 . The IC of  claim 8 , wherein the high voltage isolation component comprises a capacitor. 
     
     
         17 . The IC of  claim 8 , wherein the high voltage isolation component comprises a transformer, and wherein the top metal feature comprises a top electrode inductively coupled to an outer positioned inductance coil. 
     
     
         18 . The IC of  claim 8 , further comprising an opening through the dielectric PO layer and the crack suppressing dielectric structure that exposes the top metal feature. 
     
     
         19 . The IC of  claim 8 , wherein the PO layer touches sidewalls of the top metal feature. 
     
     
         20 . An integrated circuit (IC), comprising:
 a lower metal interconnect level over a substrate, the lower metal interconnect level including a bottom capacitor plate of a capacitor;   two or more intermediate metal interconnect levels over the lower metal interconnect level;   a metal interconnect layer of a top metal interconnect level over the two or more intermediate metal interconnect levels;   a top capacitor plate of the capacitor located in the metal interconnect layer;   a crack suppressing dielectric structure on the metal interconnect layer, the crack suppressing dielectric structure comprising at least one dielectric layer of silicon nitride (SiN) or silicon carbide (SiC); and   a dielectric passivation overcoat (PO) layer on the crack suppressing dielectric structure that touches both the PO layer and the top capacitor plate.