Redistribution Lines Having Stacking Vias

Abstract

A method includes forming a dielectric layer over a conductive feature, forming an opening in the dielectric layer, and plating a metallic material to form a redistribution line electrically coupled to the conductive feature. The redistribution line includes a via in the opening, and a metal trace. The metal trace includes a first portion directly over the via, and a second portion misaligned with the via. A first top surface of the first portion is substantially coplanar with a second top surface of the second portion of the metal trace.

What is claimed is: 
     
         1 . A method comprising:
 forming a first redistribution line over and electrically coupling to a device die, wherein the first redistribution line comprises:
 a first array of vias; and 
 a first metal trace comprising a first portion directly over and contacting the first array of vias, and a second portion vertically offset from the first array of vias; 
   forming a second redistribution line, wherein the second redistribution line comprises:
 a second array of vias comprising bottom surfaces in contact with a top surface of the first metal trace, wherein each of vias in the second array of vias overlaps one of vias in the first array of vias with a one-to-one correspondence; and 
 a second metal trace comprising a third portion directly over and contacting the second array of vias, and a fourth portion vertically offset from the second array of vias. 
   
     
     
         2 . The method of  claim 1 , wherein the forming the first array of vias and the second array of vias comprise:
 depositing a seed layer; and   performing a plating process to plate a metallic material over the seed layer.   
     
     
         3 . The method of  claim 2 , wherein the plating process has a plating rate in a range between about 0.1 μm/minute and about 1.0 μm/minute. 
     
     
         4 . The method of  claim 2 , wherein the plating process is performed using a plating current density higher than about 2.0 amps per square decimeter. 
     
     
         5 . The method of  claim 1 , wherein top surfaces of the first portion and the second portion of the first metal trace are substantially coplanar. 
     
     
         6 . The method of  claim 1  further comprising:
 encapsulating a metal post and the device die in an encapsulant, wherein the first array of vias and the second array of vias are electrically connected to the device die; and 
 planarizing the encapsulant so that the metal post penetrates through the encapsulant. 
 
     
     
         7 . The method of  claim 6 , wherein a first via in the first array of vias and a second via in the second array of vias are vertically aligned to a conductive feature in the device die. 
     
     
         8 . The method of  claim 7  further comprising, before the forming the first redistribution line, forming a third redistribution line, with the first array of vias being over and contacting the third redistribution line, wherein the third redistribution line comprises a third via contacting the conductive feature in the device die, and the first via and the second via are vertically aligned to the third via. 
     
     
         9 . The method of  claim 1  further comprising, when the first redistribution line and the second redistribution line are formed, forming a third redistribution line and a fourth redistribution line over and contacting the third redistribution line, wherein both of the third redistribution line and the fourth redistribution line are single-via redistribution lines. 
     
     
         10 . The method of  claim 9 , wherein the first redistribution line is electrically connected to a power node of the device die, and the third redistribution line is electrically connected to a signal node of the device die. 
     
     
         11 . A method comprising:
 encapsulating a conductive post and a device die in an encapsulant;   forming a conductive line comprising a via and a conductive trace over the via, wherein the via is over and in contact with the conductive post;   performing a first plating process to form a first redistribution line over and electrically connected to the conductive line, the first redistribution line comprising:
 a first array of vias; and 
 a first metal trace over and physically contacting the first array of vias; 
   performing a second plating process to form a second redistribution line comprising:
 a second array of vias comprising bottom surfaces in contact with a top surface of the first metal trace, wherein each of vias in the second array of vias overlaps one of vias in the first array of vias with a one-to-one correspondence, and wherein a first via in the first array of vias and a second via in the second array of vias are vertically aligned to the conductive post; and 
 a second metal trace comprising a third portion directly over and physically contacting the second array of vias. 
   
     
     
         12 . The method of  claim 11 , wherein the first metal trace comprises a first portion misaligned with the first array of vias. 
     
     
         13 . The method of  claim 12 , wherein the first metal trace further comprises a second portion, with the second portion being directly over and contacting the first array of vias, and wherein top surfaces of the first portion and the second portion of the first metal trace are substantially coplanar. 
     
     
         14 . The method of  claim 13 , wherein the first metal trace has a thickness, and wherein a height difference between top surfaces of the first portion and the second portion of the first metal trace is smaller than about 5 percent of the thick. 
     
     
         15 . The method of  claim 11 , wherein the first plating process has a plating rate in a range between about 1.1 μm/minute and about 1.0 μm/minute, and wherein the first plating process is performed using a plating current density higher than about 2.0 amps per square decimeter. 
     
     
         16 . The method of  claim 11 , wherein each via in the first array of vias and the second array of vias has a width smaller than about 10 μm. 
     
     
         17 . The method of  claim 11 , wherein each of the first array of vias and the second array of vias is at least a 2×2 array. 
     
     
         18 . A method comprising:
 encapsulating a device die and a metal post in an encapsulating material;   forming a plurality of redistribution lines over and electrically coupling to the device die, wherein the forming the plurality of redistribution lines comprises a plurality of plating processes, and wherein upper ones of the plurality of redistribution lines overlap corresponding lower ones of the plurality of redistribution lines, and each of the plurality of redistribution lines comprises:
 an array of vias; and 
 a metal trace over and contacting the array of vias, wherein vias in the upper ones of the plurality of redistribution lines overlap corresponding vias in the lower ones of the plurality of redistribution lines with a one-to-one correspondence. 
   
     
     
         19 . The method of  claim 18 , wherein each of the plurality of redistribution lines is formed through processes comprising:
 forming a dielectric layer;   patterning the dielectric layer to form openings in the dielectric layer;   depositing a metal seed layer extending into the openings; and   performing a corresponding one of the plurality of plating processes to deposit a metallic material.   
     
     
         20 . The method of  claim 18 , wherein the plurality of redistribution lines are electrically connected to a power node of the device die.