Semiconductor memory device and method for operating thereof

Abstract

Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a memory cell array including a plurality of memory cells;   a peripheral circuit located under the memory cell array and configured to perform an operation for the memory cell array;   wherein the peripheral circuit includes a plurality of page buffers, and the plurality of page buffers are grouped into M page buffer groups, and   wherein the page buffers are respectively coupled to M sensing lines corresponding to the M page buffer group, and at least two page buffers of each of the M page buffer groups simultaneously perform a current sensing operation via the M sensing lines, where the M is an integer greater than 0.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the operation for the memory cell array includes one of a read operation and a program verifying operation, and the current sensing operation is for the read operation or the program verifying operation. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the peripheral circuit includes a current sensing circuit, and the current sensing circuit output pass or fail signal based on the current sensing operation. 
     
     
         4 . The semiconductor device according to  claim 1 , further comprising:
 a control logic configured to control the peripheral circuit,   wherein the peripheral circuit receives an allowable bit number from the control logic, and compares the allowable bit number and a fail bit number of the current sensing operation.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein a number of the at least two page buffers simultaneously performing the current sensing operation is adjusted according to a requirement speed of the current sensing operation.