Pre-computation of memory core control signals

Abstract

An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

1 . An apparatus, comprising:
 a control circuit configured to be connected to a memory structure comprising non-volatile memory cells, the control circuit comprising a microcontroller configured to:
 determine information for generating control signals for a type of memory operation prior to receiving a request to perform a memory operation of the type of memory operation in the memory structure; 
 store the information for the type of memory operation; 
 generate the control signals based on the stored information in response to receiving a request to perform a memory operation of the type of memory operation; and 
 use the control signals generated based on the stored information to control at least one segment of the memory operation in the memory structure. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the information comprises:
 conditions that are relevant for the memory structure and from which the control signals for the type of memory operation are derivable.   
     
     
         3 . The apparatus of  claim 2 , wherein the microcontroller is configured to determine the conditions based on one or more of:
 a mode and/or a sub-mode of the memory operation;   one or more parameters that specify options to be applied during the memory operation; or   information that specifies how the flow of the control signals for the memory operation is to proceed.   
     
     
         4 . The apparatus of  claim 1 , wherein the microcontroller is further configured to:
 determine, after receiving the request, the control signals based on the stored information and information that is specific to the type of memory operation.   
     
     
         5 . The apparatus of  claim 1 , wherein the microcontroller comprises:
 a first processor configured, in response to the request to perform the memory operation, to execute a first set of instructions to form a packet that contains a flag that indicates the stored information is to be accessed; and   a second processor configured to execute a second set of instructions to access the packet, the second processor configured to execute the second set of instructions to access the stored information in response to the flag being set and to generate the control signals based on the stored information.   
     
     
         6 . The apparatus of  claim 1 , wherein the microcontroller comprises:
 a first processor configured to execute a first set of instructions to access the stored information in response to the request to perform the memory operation, the first processor configured to execute the first set of instructions to form a packet that contains the stored information; and   a second processor configured to execute a second set of instructions to access the packet, the second processor configured to execute the second set of instructions to generate the control signals based on the information in the packet.   
     
     
         7 . The apparatus of  claim 1 , wherein the information comprises:
 set/reset information that specifies a segment of the memory operation at which the control signals are to be set or reset, wherein the stored information comprises stored set/reset information.   
     
     
         8 . The apparatus of  claim 7 , wherein the microcontroller is further configured to:
 increase a voltage that is applied to a region of the memory structure at a first segment of the memory operation at which a first control signal of the control signals is set; and   decrease the voltage that is applied to the region of the memory structure at a second segment of the memory operation at which the first control signal is reset.   
     
     
         9 . The apparatus of  claim 7 , wherein the microcontroller comprises:
 a first processor configured to execute a first set of instructions to form a packet that contains a flag that indicates the stored set/reset information is to be accessed; and   a second processor configured to execute a second set of instructions to access the packet, the second processor configured to execute the second set of instructions to access the stored set/reset information and to generate the control signals based on the stored set/reset information.   
     
     
         10 . The apparatus of  claim 1 , wherein the microcontroller is further configured to:
 determine the information for generating the control signals for the type of memory operation during a power on phase of the apparatus.   
     
     
         11 . A method, comprising:
 executing instructions on a processor to compute information associated with core timing control signals that control a memory operation in a non-volatile memory structure;   storing the computed information in storage that is accessible to the processor;   accessing the stored information in response to the processor receiving a request to perform the memory operation;   setting or resetting one or more core timing control signals based on the stored information; and   using the core timing control signals to control the non-volatile memory structure during the memory operation.   
     
     
         12 . The method of  claim 11 , wherein executing instructions on the processor to compute the information associated with the core timing control signals comprises:
 computing the information based on a mode and/or a sub-mode of the memory operation.   
     
     
         13 . The method of  claim 12 , wherein executing instructions on the processor to compute the information associated with the core timing control signals further comprises:
 computing the information based on parameters that specify options to be applied during the memory operation.   
     
     
         14 . The method of  claim 13 , wherein executing instructions on the processor to compute the information associated with the core timing control signals further comprises:
 computing the information based on information that specifies how the flow of the core timing control signals is to proceed.   
     
     
         15 . The method of  claim 11 , wherein executing instructions on the processor to compute the information associated with the core timing control signals further comprises:
 computing set/reset information that indicates whether the one or more core timing control signals are to be set or reset for a segment of the memory operation.   
     
     
         16 . A non-volatile storage system, comprising:
 a die comprising a control circuit configured to be connected to a memory structure comprising non-volatile memory cells, the control circuit configured to generate and apply a set of control signals to control the memory structure to perform memory operations, the control circuit comprising:
 a first processor configured to execute first instructions to compute conditions for a sub-clock of a memory operation; and 
 a second processor configured to execute second instructions to generate control signals for the sub-clock of the memory operation based on the conditions; 
   wherein the first processor is configured to pre-compute the conditions for the sub-clock of the memory operation prior to receiving a request from a memory controller to perform the memory operation, wherein the first processor or the second processor stores the pre-computed conditions;   wherein the control circuit is configured to use the stored pre-computed conditions to generate the control signals for the sub-clock of the memory operation by at least one of:
 the first processor accessing the stored pre-computed conditions for the sub-clock of the memory operation in response to the first processor receiving a request from the memory controller to perform the memory operation, the first processor providing the stored conditions to the second processor; or 
 the second processor accessing the stored pre-computed conditions in response to a request from the first processor to access the stored pre-computed conditions, wherein the first processor requests the second processor to access the stored pre-computed conditions in response to the first processor receiving a request from the memory controller to perform the memory operation. 
   
     
     
         17 . The non-volatile storage system of  claim 16 , wherein:
 the first processor is configured to form a packet having a flag indicating that the second processor is to access the stored pre-computed conditions, wherein the first processor forms the packet in response to a request from the memory controller to perform the memory operation;   the second processor is configured to decode the packet;   the second processor is configured to access the stored pre-computed conditions; and   the second processor is configured to generate the control signals for the sub-clock based on the stored pre-computed conditions.   
     
     
         18 . The non-volatile storage system of  claim 16 , wherein:
 the first processor is configured to access the stored pre-computed conditions in response to the request from the memory controller to perform the memory operation;   the first processor is configured to form a packet having the stored pre-computed conditions that were accessed in response to the request from the memory controller to perform the memory operation;   the second processor is configured to decode the packet; and   the second processor is configured to generate the control signals for the sub-clock of the memory operation based on the pre-computed conditions in the packet.   
     
     
         19 . The non-volatile storage system of  claim 16 , wherein:
 the first processor is configured to pre-compute conditions for the sub-clock of the memory operation during a power on phase; and   the first processor is configured to store the pre-computed conditions during the power on phase.   
     
     
         20 . The non-volatile storage system of  claim 16 , wherein:
 the first processor is configured to pre-compute conditions for the sub-clock of the memory operation during a power on phase; and   the first processor is configured to instruct the second processor to store the pre-computed conditions during the power on phase.