Using fuzzy-jbit location of floating-point multiply-accumulate results

Abstract

Disclosed embodiments relate to performing floating-point (FP) arithmetic. In one example, a processor is to decode an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand, and execution circuitry to, in a first cycle, generate the FP product having a Fuzzy-Jbit format comprising a sign bit, a 9-bit exponent, and a 25-bit mantissa having two possible positions for a JBit and, in a second cycle, to accumulate the FP product with the third FP operand, while concurrently, based on Jbit positions of the FP product and the third FP operand, determining an exponent adjustment and a mantissa shift control of a result of the accumulation, wherein performing the exponent adjustment concurrently enhances an ability to perform the accumulation in one cycle.

What is claimed is: 
     
         1 . A processor comprising:
 decode circuitry to decode an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand; and   execution circuitry to execute the decoded instruction to:
 generate the FP product having a format comprising a sign bit, an exponent, and a mantissa having two adjacent bits that allow two possible positions for an implicit bit, 
 accumulate the FP product with the third FP operand, and 
 determine an exponent adjustment and a mantissa shift control of a result of the accumulation based on implicit bit positions of the FP product and the third FP operand. 
   
     
     
         2 . The processor of  claim 1 , wherein the implicit bit is an implicit 24th bit of the mantissa for a first of the two possible positions for the implicit bit, and the implicit bit is an implicit 25th bit of the mantissa for a second of the two possible positions for the implicit bit. 
     
     
         3 . The processor of  claim 1 , wherein the first, second, and third FP operands comprise packed-data vectors having multiple floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on each of the multiple elements in parallel. 
     
     
         4 . The processor of  claim 1 , wherein the first, second, and third FP operands comprise matrices having M rows by N columns of floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on a subset of the M×N elements in parallel. 
     
     
         5 . The processor of  claim 1 , wherein determining the implicit bit positions of the product and the third FP operand comprises identifying one or more possible implicit bit positions between an actual exponent and an actual fraction. 
     
     
         6 . The processor of  claim 1 , wherein a carryout, if any, of the accumulation falls into the possible implicit bit positions of the result and does not require adjusting the exponent of the result. 
     
     
         7 . The processor of  claim 1 , wherein the mantissa shift control of the result is selectable between a left-shift by one, a right-shift by one, and a no shift. 
     
     
         8 . The processor of  claim 1 , wherein the result, maintaining its format, is routed for use by a subsequent floating-point operation. 
     
     
         9 . The processor of  claim 1 , wherein the execution circuitry is to convert the result into Institute of Electronics and Electrical Engineers 754 standard format and write the converted result into a destination operand further specified by the instruction. 
     
     
         10 . A method to be performed by a processor, the method comprising:
 decoding, using decode circuitry, an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand; and   executing, using execution circuitry, the decoded instruction to:
 generate the FP product having a format comprising a sign bit, an exponent, and a mantissa having two adjacent bits that allow two possible positions for an implicit bit, 
 accumulate the FP product with the third FP operand, and, 
 determine an exponent adjustment and a mantissa shift control of a result of the accumulation based on implicit bit positions of the FP product and the third FP operand. 
   
     
     
         11 . The method of  claim 10 , wherein the implicit bit is an implicit 24th bit of the mantissa for a first of the two possible positions for the implicit bit, and the implicit bit is an implicit 25th bit of the mantissa for a second of the two possible positions for the implicit bit. 
     
     
         12 . The method of  claim 10 , wherein the first, second, and third FP operands comprise packed-data vectors having multiple floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on each of the multiple elements in parallel. 
     
     
         13 . The method of  claim 10 , wherein the first, second, and third FP operands comprise matrices having M rows by N columns of floating-point elements, and wherein the execution circuitry is to execute the decoded instruction on a subset of the M×N elements in parallel. 
     
     
         14 . The method of  claim 10 , wherein determining the implicit bit positions of the product and the third FP operand comprise identifying one or more possible implicit bit positions between an actual exponent and an actual fraction. 
     
     
         15 . The method of  claim 10 , wherein a carryout, if any, of the accumulation falls into the possible implicit bit positions of the result and does not require adjusting the exponent of the result. 
     
     
         16 . The method of  claim 10 , wherein the mantissa shift control of the result is selectable between a left-shift by one, a right-shift by one, and a no shift. 
     
     
         17 . The method of  claim 10 , wherein the result, maintaining its format, is routed for use by a subsequent floating-point operation. 
     
     
         18 . The method of  claim 10 , wherein the executing converts the result into Institute of Electronics and Electrical Engineers 754 standard format and writes the converted result into a destination operand further specified by the instruction. 
     
     
         19 . A non-transitory machine-readable medium containing code to which a processor is to respond by:
 decoding, using decode circuitry, an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand; and   executing, using execution circuitry, the decoded instruction to:
 generate the FP product having a format comprising a sign bit, an exponent, and a mantissa having two adjacent bits that allow two possible positions for an implicit bit, 
 accumulate the FP product with the third FP operand, and 
 determine an exponent adjustment and a mantissa shift control of a result of the accumulation based on implicit bit positions of the FP product and the third FP operand. 
   
     
     
         20 . The non-transitory machine-readable medium of  claim 19 , wherein the implicit bit is an implicit 24th bit of the mantissa for a first of the two possible positions for the implicit bit, and the implicit bit is an implicit 25th bit of the mantissa for a second of the two possible positions for the implicit bit. 
     
     
         21 . The non-transitory machine-readable medium of  claim 19 , wherein the mantissa shift control of the result is selectable between a left-shift by one, a right-shift by one, and a no shift. 
     
     
         22 . The non-transitory machine-readable medium of  claim 19 , wherein the result, maintaining its format, is routed for use by a subsequent floating-point operation. 
     
     
         23 . The non-transitory machine-readable medium of  claim 19 , wherein the executing converts the result into Institute of Electronics and Electrical Engineers 754 standard format and writes the converted result into a destination operand further specified by the instruction.