US2021273089A1PendingUtilityA1
Semiconductor device and fabrication method thereof
Assignee: UNITED MICROELECTRONICS CORPPriority: Jun 25, 2019Filed: May 17, 2021Published: Sep 2, 2021
Est. expiryJun 25, 2039(~12.9 yrs left)· nominal 20-yr term from priority
H10W 20/056H10W 20/039H10W 10/011H10W 10/10H10W 10/17H10W 10/0143H10D 30/024H10D 30/62H10D 84/0151H10D 84/0158H10D 84/038H10D 84/0128H01L 29/66795H01L 21/762H01L 29/785H01L 21/76852H01L 21/76877
59
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Claims
Abstract
A semiconductor device includes a substrate having at least two fins thereon and an isolation trench between the at least two fins; and an isolation structure in the isolation trench. The isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the isolation trench, and a stress-buffer film on the liner layer. The stress-buffer film is a silicon suboxide film of formula SiOy, wherein y<2.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device, comprising:
a substrate having at least two fins thereon and a first isolation trench between the at least two fins, wherein the first isolation trench is disposed within a first region; and a first isolation structure in the first isolation trench, wherein the first isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the first isolation trench, and a stress-buffer film on the liner layer, wherein the stress-buffer film is a silicon suboxide film of formula SiOy, wherein y<2.
2 . The semiconductor device of claim 1 further comprising:
a second isolation trench in the substrate within a second region; and
a second isolation structure in the second isolation trench, wherein the second isolation structure comprising the liner layer, the stress-buffer film, and a trench-fill oxide layer on the stress-buffer film.
3 . The semiconductor device of claim 2 , wherein the first region is a dense region and the second region is an isolated region.
4 . The semiconductor device of claim 2 , wherein a width of the second isolation trench is greater than that of the first isolation trench.
5 . The semiconductor device of claim 2 , wherein the liner layer is a silicon dioxide layer.
6 . The semiconductor device of claim 2 , wherein the trench-fill oxide layer may be a silicon oxide film of formula SiOx, wherein x<y.
7 . The semiconductor device of claim 1 , wherein a lower portion of the first isolation trench does not include the trench-fill oxide layer.
8 . The semiconductor device of claim 7 , wherein the lower portion is located at least below half of a trench depth of the first isolation trench within the first region.
9 . The semiconductor device of claim 1 , wherein the stress-buffer film has a thickness that is greater than or equal to about 40 angstroms at a fin pitch of about 48 nm.
10 . The semiconductor device of claim 1 , wherein the stress-buffer film has a thickness ranging between about 40 angstroms and about 80 angstroms at a fin pitch of about 48 nm.Join the waitlist — get patent alerts
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