Semiconductor package structure

Abstract

The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

What is claimed is: 
     
         1 . A semiconductor package structure, comprising:
 a semiconductor substrate having an active surface and a sidewall;   a conductive bump on the active surface, the conductive bump having a stand-off height extending along a first direction;   an encapsulant encapsulating the semiconductor substrate and encapsulating the conductive bump, wherein the encapsulant contacting the sidewall of the semiconductor substrate; and   a filler in the encapsulant, wherein a diameter of the filler along the first direction is smaller than the stand-off height.   
     
     
         2 . The semiconductor package structure of  claim 1 , wherein the filler includes a truncated filler. 
     
     
         3 . The semiconductor package structure of  claim 2 , further comprising a redistribution layer (RDL) over the conductive bump, wherein the truncated filler is in contact with the RDL. 
     
     
         4 . The semiconductor package structure of  claim 3 , wherein the RDL comprises an under bump metallization on a top thereof. 
     
     
         5 . The semiconductor package structure of  claim 4 , further comprising:
 a solder ball over the under bump metallization.   
     
     
         6 . The semiconductor package structure of  claim 3 , wherein the RDL includes a via having a diameter smaller than a diameter of the conductive bump. 
     
     
         7 . The semiconductor package structure of  claim 6 , wherein the via tapers toward the semiconductor substrate. 
     
     
         8 . The semiconductor package structure of  claim 1 , wherein the conductive bump tapers away from the semiconductor substrate. 
     
     
         9 . A semiconductor package structure, comprising:
 a semiconductor substrate having a conductive pad;   a passivation on the semiconductor substrate;   a redistribution layer (RDL) on the passivation;   a conductive bump on the redistribution layer, wherein the conductive bump has a stand-off height extending along a first direction and a projection of the conductive bump on the semiconductor substrate is spaced apart from a projection of the conductive pad on the semiconductor substrate;   an encapsulant encapsulating the semiconductor substrate and encapsulating the conductive bump; and   a filler in the encapsulant, wherein a diameter of the filler along the first direction is smaller than the stand-off height.   
     
     
         10 . The semiconductor package structure of  claim 9 , wherein the conductive bump directly contacts the RDL. 
     
     
         11 . The semiconductor package structure of  claim 9 , wherein a projection of the RDL on a surface of the semiconductor substrate is smaller than an area of the surface of the semiconductor substrate. 
     
     
         12 . The semiconductor package structure of  claim 9 , wherein the RDL contacts the passivation. 
     
     
         13 . The semiconductor package structure of  claim 9 , wherein a surface of the RDL defines a recess corresponding to the conductive pad. 
     
     
         14 . The semiconductor package structure of  claim 13 , wherein the encapsulant extends into the recess. 
     
     
         15 . The semiconductor package structure of  claim 9 , wherein the filler contacts a sidewall of the conductive bump. 
     
     
         16 . The semiconductor package structure of  claim 9 , wherein the encapsulant contacts a top surface of the passivation. 
     
     
         17 . The semiconductor package structure of  claim 9 , wherein a sidewall of the conductive bump is a curved surface. 
     
     
         18 . The semiconductor package structure of  claim 9 , wherein the encapsulant contacts a sidewall of the semiconductor substrate. 
     
     
         19 . A semiconductor package structure, comprising:
 a semiconductor substrate having an active surface and a sidewall;   a conductive pad on the active surface;   a passivation covering the pad and over the active surface;   a conductive bump on the conductive pad; and   an encapsulant encapsulating the semiconductor substrate and encapsulating the conductive bump, wherein the encapsulant contacting the sidewall of the semiconductor substrate;   wherein the semiconductor package structure having a passing rate greater than 95% to JESD22-A104G test; and   wherein a lower temperature of the JESD22-A104G test includes −40 degrees Celsius, an upper temperature of the JESD22-A104G test includes +125 degrees Celsius, and a cycling rate of the JESD22-A104G test includes between 40 to 60 minutes per cycle.   
     
     
         20 . The semiconductor package structure of  claim 19 , wherein the semiconductor package structure having a passing rate greater than 95% to JESD22-A104G test after 1000 cycles.