Gate electrode having a capping layer

Abstract

A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a semiconductor body having a top and a pair of laterally opposite sidewalls, the semiconductor body comprising germanium;   a gate stack adjacent to the top and the pair of laterally opposite sidewalls of the semiconductor body comprising germanium, the gate stack comprising:
 a gate dielectric region, the gate dielectric region comprising hafnium and oxygen; 
 a first region comprising nitrogen and silicon, wherein the gate dielectric region is between the first region and the semiconductor body; and 
 a second region comprising aluminum and titanium, wherein the first region is between the second region and the gate dielectric region; 
   a first source or drain region in the semiconductor body at a first side of the gate stack; and   a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a PMOS transistor. 
     
     
         3 . The integrated circuit structure of  claim 2 , further comprising an NMOS transistor. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a NMOS transistor. 
     
     
         5 . The integrated circuit structure of  claim 4 , further comprising a PMOS transistor. 
     
     
         6 . The integrated circuit structure of  claim 1 , wherein the second region further comprises nitrogen. 
     
     
         7 . A method for forming an integrated circuit structure, comprising:
 forming a semiconductor body having a top and a pair of laterally opposite sidewalls, the semiconductor body comprising germanium;   forming a gate stack adjacent to the top and the pair of laterally opposite sidewalls of the semiconductor body comprising germanium, forming the gate stack comprising:
 forming a gate dielectric region, the gate dielectric region comprising hafnium and oxygen; 
 forming a first region comprising nitrogen and silicon, wherein the gate dielectric region is between the first region and the semiconductor body; 
 forming a sacrificial layer, the sacrificial layer comprising polysilicon; 
 removing the sacrificial layer; and 
 forming a second region comprising aluminum and titanium, wherein the first region is between the second region and the gate dielectric region; 
   forming a first source or drain region in the semiconductor body at a first side of the gate stack; and   forming a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.   
     
     
         8 . The method of forming an integrated circuit structure of  claim 7 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a PMOS transistor. 
     
     
         9 . The method of forming an integrated circuit structure of  claim 8 , further comprising forming an NMOS transistor. 
     
     
         10 . The method of forming an integrated circuit structure of  claim 7 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a NMOS transistor. 
     
     
         11 . The method of forming an integrated circuit structure of  claim 10 , further comprising forming a PMOS transistor. 
     
     
         12 . The method of forming an integrated circuit structure of  claim 7 , wherein the second region further comprises nitrogen. 
     
     
         13 . An integrated circuit structure, comprising:
 an insulating layer;   a semiconductor body having a top and a pair of laterally opposite sidewalls, the semiconductor body comprising germanium, and the semiconductor body directly on the insulating layer;   a gate stack adjacent to the top and the pair of laterally opposite sidewalls of the semiconductor body comprising germanium, wherein a portion of the gate stack is vertically over the insulating layer, the gate stack comprising:
 a gate dielectric region, the gate dielectric region comprising hafnium and oxygen; 
 a first region comprising nitrogen and silicon, wherein the gate dielectric region is between the first region and the semiconductor body; and 
 a second region comprising aluminum and titanium, wherein the first region is between the second region and the gate dielectric region; 
   a first source or drain region in the semiconductor body at a first side of the gate stack; and   a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.   
     
     
         14 . The integrated circuit structure of  claim 13 , further comprising:
 a monocrystalline substrate, wherein the insulating layer is directly on the monocrystalline substrate.   
     
     
         15 . The integrated circuit structure of  claim 13 , wherein the portion of the gate stack is directly on the insulating layer. 
     
     
         16 . The integrated circuit structure of  claim 13 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a PMOS transistor. 
     
     
         17 . The integrated circuit structure of  claim 16 , further comprising an NMOS transistor. 
     
     
         18 . The integrated circuit structure of  claim 13 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a NMOS transistor. 
     
     
         19 . The integrated circuit structure of  claim 18 , further comprising a PMOS transistor. 
     
     
         20 . The integrated circuit structure of  claim 13 , wherein the second region further comprises nitrogen.