Semiconductor device and manufacturing method of the same

Abstract

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;   wherein the first conductive layer has a region functioning as a gate wiring,   wherein the second conductive layer has a region functioning as a source wiring,   wherein the third conductive layer has a region functioning as a drain wiring,   wherein the fifth conductive layer has a region functioning as a source wiring,   wherein in a lateral direction (a short-side direction) of the first conductive layer, the first conductive layer has a region whose width is greater than a width of the fourth conductive layer,   wherein the first conductive layer has a region that intersects with the second conductive layer,   wherein the first conductive layer has a region that intersects with the fifth conductive layer, and   wherein, when seen from a top view, the fourth conductive layer is provided between the second conductive layer and the fifth conductive layer.   
     
     
         2 . A semiconductor device comprising:
 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;   wherein the first conductive layer has a region functioning as a gate wiring,   wherein the second conductive layer has a region functioning as a source wiring,   wherein the third conductive layer has a region functioning as a drain wiring,   wherein the fourth conductive layer comprises a same material as the second conductive layer and the third conductive layer,   wherein the fourth conductive layer is in a floating state,   wherein the fifth conductive layer has a region electrically connected to a transistor located adjacent to the transistor and functioning as a source wiring,   wherein the first conductive layer has a region overlapping an entire lower surface of the fourth conductive layer,   wherein the first conductive layer has a region that intersects with the second conductive layer,   wherein the first conductive layer has a region that intersects with the fifth conductive layer, and   wherein, when seen from a top view, the fourth conductive layer is provided between the second conductive layer and the fifth conductive layer.   
     
     
         3 . A semiconductor device comprising:
 a pixel portion; and   a first connection region and a second connection region provided so as to sandwich the pixel portion, the pixel portion comprising:
 a first conductive layer, a second conductive layer, and a third conductive layer; 
   wherein the first conductive layer has a region functioning as a gate wiring,   wherein the third conductive layer has a region functioning as a source wiring,   wherein the first conductive layer has a region overlapping the second conductive layer,   wherein in a lateral direction (a short-side direction) of the first conductive layer, the first conductive layer has a region whose width is greater than a width of the second conductive layer,   wherein the first conductive layer has a region that intersects with the third conductive layer, and   wherein in the first connection region and the second connection region, an electrode opposite a pixel electrode is electrically connected to a wiring below the electrode.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein the fourth conductive layer comprises a same material as the second conductive layer and the third conductive layer. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the fourth conductive layer is capable to be in a floating state. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the fifth conductive layer has a region electrically connected to a first transistor located adjacent to a second transistor which is electrically connected to the first and third conductive layers. 
     
     
         7 . The semiconductor device according to  claim 2 , wherein in a lateral direction (a short-side direction) of the first conductive layer, the first conductive layer has a region whose width is greater than a width of the fourth conductive layer. 
     
     
         8 . The semiconductor device according to  claim 3 , wherein the first conductive layer has a region that intersects with the third conductive layer.