Embedded pad structures of three-dimensional memory devices

Abstract

Embodiments of 3D memory devices are disclosed. A disclosed 3D memory device can comprises an array interconnect layer disposed over an alternating conductor/dielectric stack and including a first array interconnect structure. Tbe 3D memory device can further comprises a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure. A pad can be embedded in the peripheral interconnect layer and electrically connected with the first peripheral device through the first peripheral interconnect structure. The array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure.

What is claimed is: 
     
         1 . A 3D memory device, comprising:
 an array interconnect layer disposed over an alternating conductor/dielectric stack and including a first array interconnect structure;   a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure; and   a pad embedded in the peripheral interconnect layer and electrically connected with the first peripheral device through the first peripheral interconnect structure;   wherein the array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure.   
     
     
         2 . The device of  claim 1 , further comprising:
 a pad opening providing an access to at least a portion of a surface of the pad.   
     
     
         3 . The device of  claim 2 , wherein the pad opening extends through the array interconnect layer and extends into the peripheral interconnect layer. 
     
     
         4 . The device of  claim 2 , wherein a depth of the pad opening is larger than a thickness of the alternating conductor/dielectric stack. 
     
     
         5 . The device of  claim 2 , further comprising:
 a plurality of channel structures each penetrating the alternating conductor/dielectric stack, wherein one of the plurality of channel structures is electrically connected with a second peripheral device below the peripheral interconnect layer through a second array interconnect structures embedded in the array interconnect layer and a second peripheral interconnect structure embedded in the peripheral interconnect layer.   
     
     
         6 . The device of  claim 2 , wherein the alternating conductor/dielectric stack includes a staircase structure, and wherein a conductive layer in the staircase structure is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure. 
     
     
         7 . The device of  claim 5 , wherein the alternating conductor/dielectric stack includes a staircase structure, and wherein a conductive layer in the staircase structure is electrically connected with a third peripheral device through a third array interconnect structures embedded in the array interconnect layer and a third peripheral interconnect structure embedded in the peripheral interconnect layer. 
     
     
         8 . A 3D memory device, comprising:
 an array interconnect layer disposed over an alternating conductor/dielectric stack;   a pad and a first array interconnect structure both embedded in the array interconnect layer and electrically connected with each other; and   a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure;   wherein the array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure, and the pad is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure.   
     
     
         9 . The device of  claim 8 , further comprising:
 a pad opening providing an access to at least a portion of a surface of the pad.   
     
     
         10 . The device of  claim 9 , wherein a depth of the pad opening is larger than a thickness of the alternating conductor/dielectric stack. 
     
     
         11 . The device of  claim 9 , further comprising:
 a plurality of channel structures each penetrating the alternating conductor/dielectric stack, wherein one of the plurality of channel structures is electrically connected with a second peripheral device below the peripheral interconnect layer through a second array interconnect structures embedded in the array interconnect layer and a second peripheral interconnect structure embedded in the peripheral interconnect layer.   
     
     
         12 . The device of  claim 9 , wherein the alternating conductor/dielectric stack includes a staircase structure, and wherein a conductive layer in the staircase structure is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure. 
     
     
         13 . The device of  claim 11 , wherein the pad opening penetrates through the alternating conductor/dielectric stack. 
     
     
         14 . The device of  claim 13 , wherein the pad opening is separated from the plurality of channel structures by a barrier structure. 
     
     
         15 . The device of  claim 13 , wherein the alternating conductor/dielectric stack includes a staircase structure, and wherein a conductive layer in the staircase structure is electrically connected with a third peripheral device through a third array interconnect structures embedded in the array interconnect layer and a third peripheral interconnect structure embedded in the peripheral interconnect layer. 
     
     
         16 . A 3D memory device, comprising:
 a pad disposed beside an alternating conductor/dielectric stack;   an array interconnect layer disposed over the alternating conductor/dielectric stack and the pad;   a first array interconnect structure embedded the array interconnect layer and electrically connected with the pad; and   a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure;   wherein the array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure, and the pad is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure.   
     
     
         17 . The device of  claim 16 , further comprising:
 a pad opening providing an access to at least a portion of a surface of the pad.   
     
     
         18 . The device of  claim 17 , further comprising:
 a plurality of channel structures each penetrating the alternating conductor/dielectric stack, wherein one of the plurality of channel structures is electrically connected with a second peripheral device below the peripheral interconnect layer through a second array interconnect structures embedded in the array interconnect layer and a second peripheral interconnect structure embedded in the peripheral interconnect layer.   
     
     
         19 . The device of  claim 17 , wherein the alternating conductor/dielectric stack includes a staircase structure, and wherein a conductive layer in the staircase structure is electrically connected with the first peripheral device through the first array interconnect structure and the first peripheral interconnect structure. 
     
     
         20 . The device of  claim 17 , wherein the alternating conductor/dielectric stack includes a staircase structure, and wherein a conductive layer in the staircase structure is electrically connected with a third peripheral device through a third array interconnect structures embedded in the array interconnect layer and a third peripheral interconnect structure embedded in the peripheral interconnect layer.