Integrated Memory Having Non-Ohmic Devices and Capacitors

Abstract

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

I/We claim: 
     
         1 . A memory cell comprising a non-ohmic device between a transistor source/drain region and a capacitor, the non-ohmic device being a non-memory element in operation. 
     
     
         2 . The memory cell of  claim 1  being a one-transistor-one-capacitor memory cell. 
     
     
         3 . The memory cell of  claim 1  wherein the capacitor is a ferroelectric capacitor. 
     
     
         4 . The memory cell of  claim 1  wherein the capacitor is a non-ferroelectric capacitor. 
     
     
         5 . The memory cell of  claim 1  wherein the transistor comprises a gate, and wherein negative voltage is not applied to said gate. 
     
     
         6 . The memory cell of  claim 1  wherein the non-ohmic device is a two-terminal select device. 
     
     
         7 . The memory cell of  claim 1  wherein the non-ohmic device is a mixed ion-electron conductor. 
     
     
         8 . The memory cell of  claim 1  wherein the non-ohmic device is an ovonic threshold switch. 
     
     
         9 . The memory cell of  claim 1  wherein the non-ohmic device is a conductive-bridging device. 
     
     
         10 . The memory cell of  claim 1  wherein the non-ohmic device is a phase change device. 
     
     
         11 . A memory cell comprising:
 a transistor having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions; and   a capacitor electrically coupled to the second source/drain region through a non-ohmic device that is a non-memory element in operation; the non-ohmic device including a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region.   
     
     
         12 . The memory cell of  claim 11  wherein the non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. 
     
     
         13 . The memory cell of  claim 11  wherein a dopant concentration within the channel region is less than or equal to about 10 17  atoms/cm 3 . 
     
     
         14 . The memory cell of  claim 11  wherein the capacitor is a ferroelectric capacitor. 
     
     
         15 . The memory cell of  claim 11  wherein the capacitor is a non-ferroelectric capacitor. 
     
     
         16 . The memory cell of  claim 11  wherein the electrical property is current. 
     
     
         17 . The memory cell of  claim 11  wherein the electrical property is voltage. 
     
     
         18 . A memory array, comprising:
 digit lines extending along a first direction;   access transistors having first source/drain regions electrically coupled with the digit lines;   wordlines operatively proximate the channel regions and extending along a second direction that crosses the first direction; and   capacitors electrically coupled with the second source/drain regions through non-ohmic devices that are non-memory elements; the capacitors being comprised by memory cells; each of the memory cells being uniquely addressed by one of the digit lines in combination with one of the wordlines.   
     
     
         19 . The memory array of  claim 18  wherein the capacitors are ferroelectric capacitors. 
     
     
         20 . The memory array of  claim 18  wherein the capacitors are non-ferroelectric capacitors.