Memory controller operating method of memory controller and memory system

Abstract

An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

What is claimed is: 
     
         1 . An apparatus comprising:
 a non-volatile memory including a plurality of memory cells; and   a control circuit in communication with the plurality of memory cells, and configured to:   perform an operation to revise a read signal based on comparisons of the numbers of memory cells in a group having a value for a data state in adjacent areas;   establish a final read signal based on a result of the operation; and   use the final read signal to distinguish between two adjacent data states stored in the group.   
     
     
         2 . The apparatus of  claim 1 , wherein the read signal is a read voltage level. 
     
     
         3 . The apparatus of  claim 1 , wherein the control circuit revises the read signal to decrease the number of error bits read from the non-volatile memory. 
     
     
         4 . The apparatus of  claim 1 , wherein the operation to revise the read signal includes:
 reading respective segments from the plurality of memory cells;   generating an output codeword based on the segments; and   performing an error correction decoding on the output codeword.   
     
     
         5 . The apparatus of  claim 1 , wherein the control circuit compares the numbers of memory cells in the group having a threshold voltage in the adjacent areas. 
     
     
         6 . The apparatus of  claim 1 , wherein the control circuit performs an error correction on data sensed from the group prior to establishing the final read signal. 
     
     
         7 . The apparatus of  claim 1 , wherein the control circuit programs the group of memory cells to a plurality of threshold voltage distributions,
 each of the plurality of threshold voltage distributions is associated with the data state,   the two adjacent data states are associated with two adjacent threshold voltage distributions, and   the control circuit searches for a minimum between the two adjacent threshold voltage distributions to revise the read signal.   
     
     
         8 . An apparatus comprising:
 a non-volatile memory including a plurality of memory cells; and   a control circuit in communication with the plurality of memory cells, and configured to:   perform an operation to revise a first signal based on comparisons of the numbers of memory cells in a group having a value for a data state in adjacent areas;   establish a second signal based on a result of the operation; and   use the second signal to distinguish between two adjacent data states stored in the group.   
     
     
         9 . The apparatus of  claim 8 , wherein the first signal is a read voltage level, and the second signal is a revised read voltage level. 
     
     
         10 . The apparatus of  claim 8 , wherein the first signal is a read threshold voltage level, and the second signal is a revised read threshold voltage level.