Apparatuses and methods for counter update operations

Abstract

The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

What is claimed is: 
     
         1 . A system, comprising:
 an array of memory cells comprising a plurality of first groups of memory cells and a plurality of second groups of memory cells; and   a memory controller coupled to the array and configured to:
 perform, responsive to receipt of a plurality of commands, corresponding memory operations sequentially on the plurality of first groups of memory cells and the plurality of second groups of memory cells; and 
 perform, independently of the plurality of commands, a counter update operation on the plurality of first groups of memory cells such that respective counters stored on one of the plurality of first groups are updated while a respective one of the corresponding memory operations is being performed on one of the plurality of second groups of memory cells. 
   
     
     
         2 . The system of  claim 1 , wherein the plurality of commands are free of instructions to cause the memory controller to update the respective counters. 
     
     
         3 . The system of  claim 1 , wherein the memory controller is configured to perform a read operation or a write operation to perform the counter update operation, wherein the counter operation is embedded within the read operation or the write operation performed by the memory controller. 
     
     
         4 . The system of  claim 1 , wherein each one of the plurality of first groups and the plurality of second groups is assigned to a respective one of a plurality of partitions, and wherein the memory controller is configured to simultaneously perform memory operations corresponding to groups of the plurality of first groups or the plurality of second groups that are assigned to different partitions. 
     
     
         5 . The system of  claim 1 , wherein the plurality of first groups or the plurality of second groups corresponds to a block of NAND memory cells and each group of the plurality of first groups or the plurality of second groups corresponds to a page of NAND memory cells. 
     
     
         6 . The system of  claim 1 , wherein the one of the plurality of first groups of memory cells further store overhead data. 
     
     
         7 . The system of  claim 6 , wherein a remaining one of the plurality of first groups of memory cells store user data. 
     
     
         8 . A system, comprising:
 a memory device comprising a plurality of groups of memory cells, wherein a first group of the plurality of groups of memory cells stores a counter associated with the plurality of groups of memory cells; and   a system controller coupled to the memory device, wherein the system controller is configured to issue a command to read data from a second group of the plurality of groups of memory cells;   wherein the memory device is configured to, in response to receipt of the command from the system controller, update the counter stored in the first group simultaneously while the data read from the second group are being transferred to the system controller.   
     
     
         9 . The system of  claim 8 , wherein the memory device is configured to perform read-modify-write (RMW) operation to update the counter without individually performing a read and a write operations to update the counter. 
     
     
         10 . The system of  claim 8 , wherein the memory device is configured to update the counter without receiving a request to update the counter from the system controller. 
     
     
         11 . The system of  claim 8 , wherein the memory device is configured to update the counter without transferring the counter back to the system controller. 
     
     
         12 . The system of  claim 8 , wherein the memory controller is configured to increment or decrement values of the respective counters until a threshold value is reached. 
     
     
         13 . The system of  claim 8 , wherein the memory controller is configured to reset values of the respective counters to an initial value in response to a determination that values of the respective counters have reached a threshold value. 
     
     
         14 . The system of  claim 8 , wherein the first group of the plurality further comprises metadata. 
     
     
         15 . The system of  claim 8 , wherein the system controller is coupled to the memory device via a memory interface compliant with Double Data Rate (DDR), Open Nand Flash Interface (ONFI), or any combination thereof. 
     
     
         16 . A method, comprising:
 receiving a plurality of commands directed to a managed unit comprising:
 a first group of memory cells storing respective counters associated with the managed unit; and 
 a second group of memory cells; and 
   performing, independently of the plurality of commands, a counter update operation on the first group while a memory operation corresponding to the managed unit is being performed on the second group.   
     
     
         17 . The method of  claim 16 , wherein performing the counter update operation further comprises performing a corresponding memory operation, in which the counter update operation is embedded, and wherein the method further comprises:
 initiating performance of the corresponding memory operation on the first group, while performing the memory operation on the second group.   
     
     
         18 . The method of  claim 16 , wherein performing, independently of the plurality of commands, the counter operation comprises incrementing or decrementing values of the respective counters until a threshold value is reached. 
     
     
         19 . The method of  claim 16 , wherein:
 the memory operation performed on the second group comprises a read-modify-write (RMW) operation; and   the method further comprises applying a write signal only to those cells of the second group whose states are to be changed during the RMW operation.   
     
     
         20 . The method of  claim 19 , wherein performing the counter update operation on the first group further comprises applying a write signal only to those cells of the first group whose states are to be changed during the RMW operation.