US2021257335A1PendingUtilityA1
Semiconductor package and method of manufacturing the same
Est. expiryFeb 19, 2040(~13.6 yrs left)· nominal 20-yr term from priority
Inventors:Shing-Yih Shih
H10W 90/22H10W 90/701H10W 74/121H10W 74/111H10W 74/014H10W 70/685H10W 70/611H10W 70/05H10W 74/142H10W 70/63H10W 90/288H10W 90/297H10W 90/20H10W 70/099H10W 72/072H10W 72/874H10W 72/9413H10W 90/00H10W 70/09H10W 90/10H10W 90/724H10W 72/241H10W 70/614H10W 74/117H01L 23/3135H01L 2225/06572H01L 23/3107H01L 21/4857H01L 21/561H01L 25/0652H01L 23/49811H01L 23/5383H01L 25/50
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Claims
Abstract
The present disclosure provides a semiconductor package. The semiconductor package includes a first die, a second die, a plurality of conductive plugs and a redistribution layer. The redistribution layer includes a first segment and a second segment electrically isolated from the first segment. The first segment of the redistribution layer electrically connects the first die to the second die, and the second segment of the redistribution layer electrically connects the first die to the conductive plugs.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor package, comprising:
at least one first die; at least one second die; a plurality of conductive plugs; and a redistribution layer comprising a first segment electrically connecting the first die to the second die and a second segment electrically isolated from the first segment to electrically connect the first die to the conductive plugs.
2 . The semiconductor package of claim 1 , wherein the first die is stacked on the second die and the conductive plugs.
3 . The semiconductor package of claim 1 , wherein the first segment of the redistribution layer is disposed between the first die and the second die, and the second segment of the redistribution layer is disposed between the first die and the conductive plugs.
4 . The semiconductor package of claim 1 , wherein the first segment of the redistribution layer is surrounded by the second segment of the redistribution layer.
5 . The semiconductor package of claim 1 , wherein the second dies are arranged horizontally to parallel the conductive plugs.
6 . The semiconductor package of claim 1 , further comprising:
a dielectric layer encasing the redistribution layer; a first insulative material surrounding the first die; and a second insulative material surrounding the second die and the conductive plugs.
7 . The semiconductor package of claim 1 , further comprising:
a passivation layer covering the second die and the conductive plugs; a conductive layer penetrating through the passivation layer and comprising a first portion connected to the second die and a second portion connected to the conductive plugs; and a plurality of solder bumps mounted on the conductive layer.
8 . A method of manufacturing a semiconductor package assembly, comprising:
providing a plurality of first dies arranged horizontally; forming a redistribution layer electrically coupled to the first dies, wherein the redistribution layer is divided into a first segment and a second segment electrically isolated from the first segment; mounting a plurality of second dies on the first segment of the redistribution layer; depositing a second insulative layer on the second dies and the redistribution layer; and forming a plurality of conductive plugs penetrating through the second insulative material and contacting the second segment of the redistribution layer.
9 . The method of claim 8 , further comprising forming at least one dielectric layer to encase the redistribution layer.
10 . The method of claim 8 , further comprising:
depositing a passivation layer on the second dies, the conductive plugs and the second insulating layers; forming a conductive layer penetrating through the passivation layer, wherein the conductive layer comprises a first portion electrically coupled to the second dies and a second portion electrically isolated from the first portion and contacting the conductive plugs; and forming a plurality of solder bumps connected to the conductive layer.
11 . The method of claim 10 , further comprising performing a grinding process to expose conductive lines of the second dies before the deposition of the passivation layer.
12 . The method of claim 8 , wherein a melting point of the first insulative material is greater than that of the second insulative material.
13 . The method of claim 8 , wherein the first dies have a first distance therebetween, the second dies have a second distance therebetween, and the second distance is less than the first distance.
14 . The method of claim 8 , wherein the first segment is disposed at central portion of the redistribution layer, and the second segment surrounds the first segment.
15 . The method of claim 8 , wherein the first dies and the second dies are symmetric with respect to a central axis of the semiconductor package.
16 . The method of claim 8 , further comprising molding the first dies with a first insulative material before the formation of the redistribution layer.Join the waitlist — get patent alerts
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