Semiconductor package

Abstract

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a redistribution layer;   a semiconductor chip provided on the redistribution layer and having a first surface and a second surface opposite to the first surface, the semiconductor chip including a first chip pad and a second chip pad which are exposed at the first surface;   a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad;   an insulating layer covering the first surface and the capacitor chip; and   a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer,   wherein the conductive post is spaced apart from the capacitor chip.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the capacitor chip comprises a base substrate, a capacitor layer, and an interconnection layer. 
     
     
         3 . The semiconductor package of  claim 1 , wherein a ratio of a maximum width of the capacitor chip in a first direction parallel to the first surface to a maximum width of the semiconductor chip in the first direction ranges from 0.05 to 0.2. 
     
     
         4 . The semiconductor package of  claim 1 , wherein a maximum width of the capacitor chip in a first direction parallel to the first surface ranges from 0.1 mm to 1 mm. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the first chip pad is in contact with the capacitor chip pad. 
     
     
         6 . The semiconductor package of  claim 1 , further comprising:
 a first connection portion disposed between the first chip pad and the capacitor chip pad; and   a first underfill pattern sealing the first connection portion,   wherein the first connection portion is in contact with the first chip pad and the capacitor chip pad.   
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 a molding pattern provided on the redistribution layer and covering the semiconductor chip,   wherein the redistribution layer extends onto a bottom surface of the molding pattern.   
     
     
         8 . The semiconductor package of  claim 7 , further comprising:
 an upper redistribution pattern on a top surface of the molding pattern.   
     
     
         9 . The semiconductor package of  claim 1 , further comprising:
 a connection substrate provided on the redistribution layer and having a hole penetrating the connection substrate,   wherein the semiconductor chip and the capacitor chip are provided in the hole.   
     
     
         10 . The semiconductor package of  claim 1 , further comprising:
 a molding pattern provided on the redistribution layer and encapsulating the semiconductor chip; and   a conductive structure penetrating the molding pattern and extending vertically,   wherein a sidewall of the conductive structure is substantially parallel to a sidewall of the molding pattern.   
     
     
         11 . A semiconductor package comprising:
 a redistribution layer;   a first semiconductor chip provided on the redistribution layer and having a first surface and a second surface opposite to the first surface, the first semiconductor chip including a first chip pad and a second chip pad which are exposed at the first surface;   a capacitor chip covering the first surface and disposed between the first surface and the redistribution layer, the capacitor chip including a capacitor chip pad connected to the first chip pad; and   a through-structure penetrating the capacitor chip and connecting the second chip pad to the redistribution layer,   wherein a sidewall of the capacitor chip is vertically aligned with a sidewall of the first semiconductor chip.   
     
     
         12 . The semiconductor package of  claim 11 , further comprising:
 a liner layer covering an inner sidewall of a through-hole penetrating the capacitor chip,   wherein the through-structure is disposed in the through-hole, and   wherein the through-structure comprises a barrier pattern and a conductive pattern filling the through-hole.   
     
     
         13 . The semiconductor package of  claim 11 ,
 wherein the capacitor chip comprises a base substrate including silicon, a capacitor layer, and an interconnection layer, and   wherein the interconnection layer exposes the capacitor chip pad.   
     
     
         14 . The semiconductor package of  claim 11 , wherein the first chip pad is in contact with the capacitor chip pad. 
     
     
         15 . The semiconductor package of  claim 11 , further comprising:
 a molding pattern provided on the redistribution layer and covering the first semiconductor chip,   wherein the redistribution layer extends onto a bottom surface of the molding pattern.   
     
     
         16 . The semiconductor package of  claim 15 , further comprising:
 an upper redistribution pattern on a top surface of the molding pattern.   
     
     
         17 . The semiconductor package of  claim 16 , further comprising:
 a package substrate, a second semiconductor chip, and an upper molding pattern, which are provided on the upper redistribution pattern,   wherein the second semiconductor chip includes a memory chip.   
     
     
         18 . The semiconductor package of  claim 11 , further comprising:
 a connection substrate provided on the redistribution layer and having a hole penetrating the connection substrate,   wherein the first semiconductor chip and the capacitor chip are provided in the hole.   
     
     
         19 . A semiconductor package comprising:
 a redistribution layer comprising redistribution patterns and insulating patterns;   a semiconductor chip provided on the redistribution layer and having a first surface and a second surface opposite to the first surface, the semiconductor chip including first chip pads and a second chip pad which are exposed at the first surface;   a plurality of capacitor chips disposed between the first surface and the redistribution layer and including capacitor chip pads connected to the first chip pads;   an insulating layer covering the first surface and the capacitor chips;   a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer, the conductive post spaced apart from the capacitor chips;   a molding pattern provided on the redistribution layer and covering the semiconductor chip;   a first connection pad provided on the redistribution layer, and a second connection pad provided on a bottom surface of the insulating layer;   a connection portion disposed between the first connection pad and the second connection pad;   a connection substrate provided on the redistribution layer and having a hole penetrating the connection substrate, wherein the semiconductor chip and the capacitor chips are provided in the hole; and   an upper redistribution pattern provided on a top surface of the molding pattern.   
     
     
         20 . The semiconductor package of  claim 19 , wherein the connection substrate comprises a conductive structure, and
 wherein the conductive structure electrically connects the upper redistribution pattern and the redistribution layer to each other.