Landing pad in interconnect and memory stacks: structure and formation of the same

Abstract

A conductive landing pad structure is formed utilizing a selective deposition process on a surface of an electrically conductive structure that is embedded in a first dielectric material layer. The conductive landing pad structure is located on an entirety of a surface of the electrically conductive structure and does not extend onto the first dielectric material layer. A conductive metal-containing structure is formed on a physically exposed surface of the conductive landing pad structure. During the formation of the conductive metal-containing structure which includes ion beam etching and/or a wet chemical etch, no conductive landing pad material particles re-deposit on the sidewalls of the conductive metal-containing structure.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 an electrically conductive structure embedded in a first dielectric material layer;   a conductive landing pad structure located on an entirety of a surface of the electrically conductive structure;   a conductive metal-containing structure located on an entirety of a surface of the conductive landing pad structure; and   a contact structure contacting at least one surface of the conductive metal-containing structure, wherein the conductive landing pad structure, the conductive metal-containing structure, and the contact structure are embedded in a second dielectric material layer that is present above the first dielectric material layer, and wherein the conductive metal-containing structure has a sidewall devoid of re-deposited conductive landing pad material particles.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the sidewall of the conductive metal-containing structure is vertically aligned to a sidewall of the conductive landing pad structure. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the first dielectric material layer has a recessed surface compared to a topmost surface of the conductive landing pad structure. 
     
     
         4 . The semiconductor structure of  claim 3 , further comprising a spacer located on sidewalls of the electrically conductive structure, the conductive landing pad structure and the conductive metal-containing structure. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the conductive metal-containing structure is composed of an electrically conductive metal or metal alloy. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the metal-containing structure is composed of a non-volatile memory stack. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein the non-volatile memory stack includes a ferroelectric (FE) memory stack, a resistive random access memory (ReRAM) stack, a magnetoresistive random access memory (MRAM) stack, or a phase change random access memory (PRAM) stack. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the least one surface of the conductive metal-containing structure is a topmost surface. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the least one surface of the conductive metal-containing structure is a topmost surface and a sidewall surface. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein the contact structure has a topmost surface that is coplanar with a topmost surface of the second dielectric material layer. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising a substrate located beneath the first dielectric material layer, wherein the substrate comprises a front-end-of-the-line level. 
     
     
         12 . The semiconductor structure of  claim 1 , further comprising a spacer located along an upper portion of a sidewall of the electrically conductive structure, an entirety of a sidewall of the conductive landing pad structure, and only a lower portion of the sidewall of the conductive metal-containing structure. 
     
     
         13 . The semiconductor structure of  claim 12 , wherein a portion of the contact structure directly contacts an upper portion of the sidewall of the conductive metal-containing structure. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein the spacer has a bottommost surface contacting a topmost surface of the first dielectric material layer. 
     
     
         15 . The semiconductor structure of  claim 12 , wherein the spacer has a bottom width that is greater than a top width. 
     
     
         16 . The semiconductor structure of  claim 1 , wherein the contact structure has a width greater than a width of each of the metal-containing structure, the conductive landing pad structure, and the electrically conductive structure. 
     
     
         17 . A semiconductor structure comprising:
 an electrically conductive structure embedded in a first dielectric material layer;   a conductive landing pad structure located on an entirety of a surface of the electrically conductive structure;   a magnetic tunnel junction structure located on an entirety of a surface of the conductive landing pad structure; and   a contact structure contacting at least one surface of the magnetic tunnel junction structure, wherein the conductive landing pad structure, the magnetic tunnel junction structure, and the contact structure are embedded in a second dielectric material layer that is present above the first dielectric material layer, and wherein the magnetic tunnel junction structure has a sidewall devoid of re-deposited conductive landing pad material particles.   
     
     
         18 . The semiconductor structure of  claim 17 , further comprising a spacer located along an upper portion of a sidewall of the electrically conductive structure, an entirety of a sidewall of the conductive landing pad structure, and only a lower portion of the sidewall of the magnetic tunnel junction structure. 
     
     
         19 . The semiconductor structure of  claim 18 , wherein a portion of the contact structure directly contacts an upper portion of the sidewall of the magnetic tunnel junction structure. 
     
     
         20 . The semiconductor structure of  claim 18 , wherein the spacer has a bottommost surface contacting a topmost surface of the first dielectric material layer.