Gate electrode having a capping layer

Abstract

A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a semiconductor body;   a gate stack over the semiconductor body, the gate stack comprising:
 a gate dielectric layer, the gate dielectric layer comprising hafnium and oxygen; 
 a first layer above the gate dielectric layer, the first layer comprising nitrogen and silicon; and 
 a second layer above the first layer, the second layer comprising aluminum and titanium; 
   a first source or drain region in the semiconductor body at a first side of the gate stack; and   a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a PMOS transistor. 
     
     
         3 . The integrated circuit structure of  claim 2 , further comprising an NMOS transistor. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a NMOS transistor. 
     
     
         5 . The integrated circuit structure of  claim 4 , further comprising a PMOS transistor. 
     
     
         6 . A method for forming an integrated circuit structure, comprising:
 forming a semiconductor body;   forming a gate stack over the semiconductor body, forming the gate stack comprising:
 forming a gate dielectric layer, the gate dielectric layer comprising hafnium and oxygen; 
 forming a first layer above the gate dielectric layer, the first layer comprising nitrogen and silicon; 
 forming a sacrificial layer, the sacrificial layer comprising polysilicon; 
 removing the sacrificial layer; and 
 forming a second layer above the first layer, the second layer comprising aluminum and titanium; 
   forming a first source or drain region in the semiconductor body at a first side of the gate stack; and   forming a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.   
     
     
         7 . The method of forming an integrated circuit structure of  claim 6 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a PMOS transistor. 
     
     
         8 . The method of forming an integrated circuit structure of  claim 7 , further comprising forming an NMOS transistor. 
     
     
         9 . The method of forming an integrated circuit structure of  claim 6 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a NMOS transistor. 
     
     
         10 . The method of forming an integrated circuit structure of  claim 9 , further comprising forming a PMOS transistor. 
     
     
         11 . An integrated circuit structure, comprising:
 a semiconductor body;   a gate stack over the semiconductor body, the gate stack comprising:
 a gate dielectric region, the gate dielectric region comprising hafnium and oxygen; 
 a first region above the gate dielectric region, the first region comprising nitrogen and silicon; and 
 a second region above the first region, the second region comprising aluminum and titanium; 
   a first source or drain region in the semiconductor body at a first side of the gate stack; and   a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.   
     
     
         12 . The integrated circuit structure of  claim 11 , wherein the second region further comprises tantalum. 
     
     
         13 . The integrated circuit structure of  claim 11 , wherein the second region further comprises carbon. 
     
     
         14 . The integrated circuit structure of  claim 11 , wherein the second region further comprises nitrogen. 
     
     
         15 . The integrated circuit structure of  claim 11 , wherein the second region further comprises tungsten. 
     
     
         16 . The integrated circuit structure of  claim 11 , wherein the second region further comprises tantalum, nitrogen, and tungsten. 
     
     
         17 . The integrated circuit structure of  claim 11 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a PMOS transistor. 
     
     
         18 . The integrated circuit structure of  claim 17 , further comprising an NMOS transistor. 
     
     
         19 . The integrated circuit structure of  claim 11 , wherein the semiconductor body, the gate stack, the first source or drain region and the second source or drain region are all part of a NMOS transistor. 
     
     
         20 . The integrated circuit structure of  claim 19 , further comprising a PMOS transistor. 
     
     
         21 . The integrated circuit structure of  claim 11 , wherein the semiconductor body and the gate stack are on the top surface and sidewalls of the semiconductor body.