Through gate fin isolation

Abstract

Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction;   an isolation structure separating a first portion of the fin from a second portion of the fin along the first direction, the isolation structure having a width along the first direction;   a first gate structure comprising a first gate electrode over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin, and the first gate structure further comprising a first high-k dielectric layer between the first gate electrode and the first portion of the fin and along sidewalls of the first gate electrode, wherein the first gate structure has the width along the first direction, and wherein a center of the first gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction;   a second gate structure comprising a second gate electrode over the top of and laterally adjacent to the sidewalls of a first region of the second portion of the fin, and the second gate structure further comprising a second high-k dielectric layer between the second gate electrode and the second portion of the fin and along sidewalls of the second gate electrode, wherein the second gate structure has the width along the first direction, and wherein a center of the second gate structure is spaced apart from the center of the isolation structure by the pitch along the first direction;   a third gate structure comprising a third gate electrode over the top of and laterally adjacent to the sidewalls of a second region of the second portion of the fin, and the third gate structure further comprising a third high-k dielectric layer between the third gate electrode and the second portion of the fin and along sidewalls of the third gate electrode, wherein the third gate structure has the width along the first direction, and wherein a center of the third gate structure is spaced apart from the center of the second gate structure by the pitch along the first direction;   a first epitaxial semiconductor region on the first portion of the fin between the first gate structure and the isolation structure;   a second epitaxial semiconductor region on the second portion of the fin between the second gate structure and the isolation structure; and   a third epitaxial semiconductor region on the second portion of the fin between the second gate structure and the third gate structure.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the first epitaxial semiconductor region has a width along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first portion of the fin along the second direction beneath the first gate structure. 
     
     
         3 . The integrated circuit structure of  claim 2 , wherein the second epitaxial semiconductor region has a width along the second direction wider than a width of the second portion of the fin along the second direction beneath the second gate structure. 
     
     
         4 . The integrated circuit structure of  claim 3 , wherein the third epitaxial semiconductor region has a width along the second direction wider than the width of the second portion of the fin along the second direction beneath the second gate structure. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the isolation structure separating the first portion of the fin from the second portion of the fin along the first direction induces a stress on the first portion of the fin and on the second portion of the fin. 
     
     
         6 . The integrated circuit structure of  claim 5 , wherein the stress is a compressive stress. 
     
     
         7 . The integrated circuit structure of  claim 5 , wherein the stress is a tensile stress. 
     
     
         8 . The integrated circuit structure of  claim 1 , wherein the fin further comprises germanium. 
     
     
         9 . The integrated circuit structure of  claim 1 , wherein the isolation structure has a top substantially co-planar with a top of the first gate structure, with a top of the second gate structure, and with a top of the third gate structure. 
     
     
         10 . The integrated circuit structure of  claim 1 , wherein the fin has a crystallographic continuity with a semiconductor substrate. 
     
     
         11 . The integrated circuit structure of  claim 1 , wherein the first epitaxial semiconductor region, the second epitaxial semiconductor region, and the third epitaxial semiconductor region are embedded epitaxial semiconductor regions. 
     
     
         12 . An integrated circuit structure, comprising:
 a fin comprising silicon;   an isolation structure above the fin and extending into the fin, the isolation structure separating a first portion of the fin from a second portion of the fin, the isolation structure having an upper surface;   a first gate structure over the first portion of the fin, the first gate structure having an upper surface co-planar with the upper surface of the isolation structure;   a first source or drain structure in the first portion of the fin, the first source or drain structure between the isolation structure and the first gate structure;   a second gate structure over the second portion of the fin, the second gate structure having an upper surface co-planar with the upper surface of the isolation structure; and   a second source or drain structure in the second portion of the fin, the second source or drain structure between the isolation structure and the second gate structure.   
     
     
         13 . The integrated circuit structure of  claim 12 , further comprising:
 a third gate structure over the second portion of the fin, the third gate structure having an upper surface co-planar with the upper surface of the isolation structure.   
     
     
         14 . The integrated circuit structure of  claim 13 , further comprising:
 a third source or drain structure in the second portion of the fin, the third source or drain structure between the second gate structure and the third gate structure.   
     
     
         15 . The integrated circuit structure of  claim 12 , wherein the first gate structure and the second gate structure each comprise a gate dielectric and a gate electrode. 
     
     
         16 . The integrated circuit structure of  claim 12 , wherein the isolation structure separating the first portion of the fin from the second portion of the fin induces a stress on the first portion of the fin and on the second portion of the fin. 
     
     
         17 . The integrated circuit structure of  claim 16 , wherein the stress is a compressive stress. 
     
     
         18 . The integrated circuit structure of  claim 16 , wherein the stress is a tensile stress. 
     
     
         19 . An integrated circuit structure, comprising:
 a fin comprising silicon;   an isolation structure through the fin, the isolation structure separating a first portion of the fin from a second portion of the fin, and the isolation structure having a first side, a second side, and a center;   a first gate structure over the first portion of the fin, the first gate structure a nearest gate structure to the first side of the isolation structure, the first gate structure having a center, the center of the first gate structure spaced apart from the center of the isolation structure by a first distance;   a first epitaxial source or drain structure in the first portion of the fin, the first epitaxial source or drain structure between the isolation structure and the first gate structure;   a second gate structure over the second portion of the fin, the second gate structure a nearest gate structure to the second side of the isolation structure, the second gate structure having a center, the center of the second gate structure spaced apart from the center of the isolation structure by a second distance, the second distance substantially the same as the first distance; and   a second epitaxial source or drain structure in the second portion of the fin, the second epitaxial source or drain structure between the isolation structure and the second gate structure.   
     
     
         20 . The integrated circuit structure of  claim 19 , further comprising:
 a third gate structure over the second portion of the fin, the third gate structure having a center, the center of the third gate structure spaced apart from the center of the second gate structure by a third distance, the third distance substantially the same as the first distance.   
     
     
         21 . The integrated circuit structure of  claim 20 , further comprising:
 a third epitaxial source or drain structure in the second portion of the fin, the third epitaxial source or drain structure between the second gate structure and the third gate structure.   
     
     
         22 . The integrated circuit structure of  claim 19 , wherein the first gate structure and the second gate structure each comprise a gate dielectric and a gate electrode. 
     
     
         23 . The integrated circuit structure of  claim 19 , wherein the isolation structure separating the first portion of the fin from the second portion of the fin induces a stress on the first portion of the fin and on the second portion of the fin. 
     
     
         24 . The integrated circuit structure of  claim 23 , wherein the stress is a compressive stress. 
     
     
         25 . The integrated circuit structure of  claim 23 , wherein the stress is a tensile stress.