Semiconductor device, display device, and electronic device

Abstract

An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first housing;   a second housing;   a hinge; and   a display panel overlapping with the first housing and the second housing, the display panel comprising a first display region overlapping with the first housing and a second display region overlapping with the second housing,   wherein first image data is output to the first display region,   wherein second data is output to the second display region, and   wherein the first image data and the second image data are different from each other.   
     
     
         2 . A semiconductor device comprising:
 a first housing;   a second housing;   a hinge; and   a display panel overlapping with the first housing and the second housing, the display panel comprising a first display region overlapping with the first housing and a second display region overlapping with the second housing,   wherein a level of luminance and color tones of the first display region and the second display region are individually set.   
     
     
         3 . A semiconductor device comprising:
 a plurality of sensors,   a first housing;   a second housing;   a hinge; and   a display panel overlapping with the first housing and the second housing, the display panel comprising a first display region overlapping with the first housing and a second display region overlapping with the second housing,   wherein data output to a first display element in the first display region and date output to a second display element in the first region are different from each other.   
     
     
         4 . The semiconductor device according to  claim 1 , further comprising:
 a plurality of retention circuits comprising a first transistor and a first capacitor,   wherein a channel formation region of the first transistor comprises a metal oxide.   
     
     
         5 . The semiconductor device according to  claim 2 , further comprising:
 a plurality of retention circuits comprising a first transistor and a first capacitor,   wherein a channel formation region of the first transistor comprises a metal oxide.   
     
     
         6 . The semiconductor device according to  claim 3 , further comprising:
 a plurality of retention circuits comprising a first transistor and a first capacitor,   wherein a channel formation region of the first transistor comprises a metal oxide.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein the first image data and the second image data are generated in accordance with an angle formed between the first housing and the second housing. 
     
     
         8 . The semiconductor device according to  claim 2 , wherein the level of luminance and the color tones of the first display region and the second display region are set in accordance with an angle formed between the first housing and the second housing. 
     
     
         9 . The semiconductor device according to  claim 6 , further comprising:
 a frame memory comprising a plurality of memory cells, each of the plurality of memory cells comprising a second transistor and a second capacitor,   wherein the second transistor is configured to control charging and discharging of the second capacitor, and   wherein a channel formation region of the second transistor comprises a metal oxide.   
     
     
         10 . The semiconductor device according to  claim 7 , further comprising:
 a first controller; and   a second controller,   wherein the second controller is configured to generate a timing signal, and   wherein a register is configured to store a parameter for generating the timing signal in the second controller.   
     
     
         11 . The semiconductor device according to  claim 8 , further comprising:
 a first controller; and   a second controller,   wherein the second controller is configured to generate a timing signal, and   wherein a register is configured to store a parameter for generating the timing signal in the second controller.   
     
     
         12 . The semiconductor device according to  claim 10 , wherein the first controller is configured to control power supply to the second controller. 
     
     
         13 . The semiconductor device according to  claim 11 , wherein the first controller is configured to control power supply to the second controller. 
     
     
         14 . The semiconductor device according to  claim 12 , further comprising a third controller,
 wherein the third controller is configured to receive a first signal from an optical sensor, and to generate, on the basis of the first signal, a second signal for performing processing in an image processing portion.   
     
     
         15 . The semiconductor device according to  claim 13 , further comprising a third controller,
 wherein the third controller is configured to receive a first signal from an optical sensor, and to generate, on the basis of the first signal, a second signal for performing processing in an image processing portion.