Neuro-Processing Circuit Using Three-Dimensional Memory to Store Look-Up Table of Activation Function

Abstract

A neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises a neuro-storage circuit and a neuro-processing circuit. The neuro-processing circuit comprises a multiplier disposed on a semiconductor substrate and a three-dimensional memory (3D-M) array stacked above the multiplier. The 3D-M array stores at least a portion of a look-up table (LUT) of an activation function and at least partially overlaps the multiplier.

What is claimed is: 
     
         1 . A neuro-processing circuit on a semiconductor substrate, comprising:
 a multiplier disposed on said semiconductor substrate;   at least a three-dimensional memory (3D-M) array stacked above said multiplier for storing at least a portion of a look-up table (LUT) of an activation function;   wherein said 3D-M array at least partially overlaps said multiplier; and, an output of said multiplier is communicatively coupled with an input of said 3D-M array.   
     
     
         2 . The neuro-processing circuit according to  claim 1 , wherein said 3D-M is a three-dimensional read-only memory (3D-ROM). 
     
     
         3 . The neuro-processing circuit according to  claim 2 , wherein said 3D-ROM is a non-volatile memory (NVM). 
     
     
         4 . The neuro-processing circuit according to  claim 2 , wherein said 3D-ROM is a three-dimensional printed memory (3D-P). 
     
     
         5 . The neuro-processing circuit according to  claim 4 , wherein data are fixedly recorded in said 3D-P. 
     
     
         6 . The neuro-processing circuit according to  claim 5 , wherein data are recorded by photo-lithography. 
     
     
         7 . The neuro-processing circuit according to  claim 5 , wherein data are recorded by nano-imprint. 
     
     
         8 . The neuro-processing circuit according to  claim 5 , wherein data are recorded by e-beam lithography. 
     
     
         9 . The neuro-processing circuit according to  claim 5 , wherein data are recorded by DUV lithography. 
     
     
         10 . The neuro-processing circuit according to  claim 5 , wherein data are recorded by laser-programming. 
     
     
         11 . The neuro-processing circuit according to  claim 1 , further comprising an adder on said semiconductor substrate. 
     
     
         12 . The neuro-processing circuit according to  claim 1 , further comprising a multiplier accumulator (MAC) on said semiconductor substrate. 
     
     
         13 . The neuro-processing circuit according to  claim 1 , further comprising a pre-processor on said semiconductor substrate. 
     
     
         14 . The neuro-processing circuit according to  claim 1 , further comprising an X-decoder for said 3D-M array on said semiconductor substrate. 
     
     
         15 . The neuro-processing circuit according to  claim 1 , further comprising a Y-decoder for said 3D-M array on said semiconductor substrate. 
     
     
         16 . The neuro-processing circuit according to  claim 1 , wherein all memory cells of said 3D-M array are not disposed on said semiconductor substrate. 
     
     
         17 . The neuro-processing circuit according to  claim 13 , wherein an output of said multiplier is communicatively coupled with said pre-processor. 
     
     
         18 . The neuro-processing circuit according to  claim 14 , wherein an output of said multiplier is communicatively coupled with said X-decoder. 
     
     
         19 . The neuro-processing circuit according to  claim 15 , wherein an output of said Y-decoder is a result of said neuro-processing circuit. 
     
     
         20 . The neuro-processing circuit according to  claim 1 , further comprising a plurality of contact vias for communicatively coupling said multiplier and said 3D-M array.