Multi-mode nmve over fabrics devices

Abstract

A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

What is claimed is: 
     
         1 . A device, comprising:
 a connector to connect the device to a component in a storage system;   a mode of operation selection circuitry configured to receive a signal via the connector, the signal indicating a selection of a first mode of operation from at least the first mode of operation and a second mode of operation; and   mode configuration circuitry to configure the device to use the first mode of operation based at least in part on the mode of operation selection circuitry,   wherein the first mode of operation includes a first protocol to communicate between the device and the storage system, and   wherein the second mode includes a second protocol to communicate between the device and the storage system.   
     
     
         2 . The device according to  claim 1 , wherein the mode of operation selection circuitry is configured to determine the first mode of operation from the signal via a pin on the connector. 
     
     
         3 . The device according to  claim 1 , wherein the connector supports a plurality of Peripheral Component Interconnect Express (PCIe) lanes and Serial Attached Small Computer System Interface (SCSI) (SAS) pins. 
     
     
         4 . The device according to  claim 3 , wherein, based at least in part on the first mode of operation being an Non-Volatile Memory Express (NVMe) mode of operation, the second circuitry is configured to use two lanes of the PCIe lanes as both a data plane and a control plane for a host and to disable use of an Ethernet port via the SAS pins. 
     
     
         5 . The device according to  claim 3 , wherein, based at least in part on the first mode of operation being an Non-Volatile Memory Express over Fabric (NVMeoF) mode of operation, the second circuitry is configured to use two lanes of the PCIe lanes as a control plane for a host, and to use a set of SAS pins as an Ethernet port for a data plane for the host. 
     
     
         6 . A method, comprising:
 receiving a signal at a device via a connector connecting the device with a component in a storage system;   determining a first mode of operation based at least in part on the signal; and   configuring the device to enable the first mode of operation and to disable a second mode of operation.   
     
     
         7 . The method according to  claim 6 , wherein determining the first mode of operation based at least in part on the signal includes accessing the signal from a pin on the connector. 
     
     
         8 . The method according to  claim 6 , wherein configuring the device to enable the first mode of operation and to disable the second mode of operation includes, based at least in part on the first mode of operation including a Non-Volatile Memory Express (NVMe) mode of operation:
 enabling two Peripheral Component Interconnect Express (PCIe) lanes as both a data plane and a control plane for a host; and   disabling an Ethernet port for the host.   
     
     
         9 . The method according to  claim 6 , wherein configuring the device to enable the first mode of operation and to disable the second mode of operation includes, based at least in part on the first mode of operation including a Non-Volatile Memory Express over Fabric (NVMeoF) mode of operation:
 enabling two PCIe lanes as a control plane for a host; and   enabling an Ethernet port as a data plane for the host using a pair of SAS pins on the connector as the Ethernet port.   
     
     
         10 . A storage system, comprising:
 a device; and   a component connected to the device, the component configured to send a signal to the device specifying a first mode of operation,   wherein the device is capable of supporting the first mode of operation and a second mode of operation; and   wherein the device is configured to enable the first mode of operation and disable the second mode of operation.   
     
     
         11 . The storage system according to  claim 10 , wherein the component is configured to send the signal to the device using at least one pin on a connector of the device. 
     
     
         12 . The storage system according to  claim 10 , wherein:
 the first mode of operation includes a Non-Volatile Memory Express (NVMe) mode of operation; and   the connector supports a Peripheral Component Interconnect Express (PCIe) bus connected to the device, the PCIe bus including two PCIe lanes as both a data plane and a control plane.   
     
     
         13 . The storage system according to  claim 10 , wherein:
 the first mode of operation includes a Non-Volatile Memory Express over Fabric (NVMeoF) mode of operation;   the connector supports a PCIe bus connected to the device, the PCIe bus including two PCIe lanes as a data plane; and   the connector includes an Ethernet port as a control plane.   
     
     
         14 . The storage system according to  claim 10 , wherein:
 the storage system further comprises a memory storing a Vital Product Data (VPD); and   the component is configured to read the first mode of operation from the VPD before sending the signal to the device.