Display device and manufacturing method thereof

Abstract

A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer and including a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a breadth of the first opening is different than a breadth of the second opening, and a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.

What is claimed is: 
     
         1 . A display device comprising:
 a substrate;   a first conductive layer on the substrate;   a first insulating layer on the first conductive layer;   an active pattern on the first insulating layer and including a semiconductor material;   a second insulating layer on the active pattern; and   a second conductive layer on the second insulating layer,   wherein the first insulating layer has a first opening exposing the first conductive layer,   the second insulating layer has a second opening exposing the first conductive layer,   the first opening is different in breadth from the second opening, and   a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.   
     
     
         2 . The display device of  claim 1 , wherein:
 the second conductive layer comprises a first electrode, and   the first electrode is electrically connected to the first conductive layer through the second opening.   
     
     
         3 . The display device of  claim 2 , wherein:
 the second insulating layer has a third opening exposing the active pattern, and   the first electrode is electrically connected to the active pattern through the third opening.   
     
     
         4 . The display device of  claim 1 , further comprising:
 a third insulating layer on the active pattern; and   a third conductive layer on the third insulating layer,   wherein no other conductive layer is between the second conductive layer and the third conductive layer in a sectional view.   
     
     
         5 . The display device of  claim 4 , wherein a side surface of the third insulating layer is aligned with a side surface of the third conductive layer. 
     
     
         6 . The display device of  claim 1 , wherein:
 the first conductive layer comprises a conductive pattern overlapping the active pattern,   the second conductive layer comprises a pixel electrode electrically connected to the conductive pattern through the second opening, and   the display device further comprises an emission layer and a common electrode on the pixel electrode.   
     
     
         7 . The display device of  claim 1 , wherein:
 the first conductive layer comprises a data line, and   the second conductive layer comprises a connecting member electrically connected to the data line through the second opening.   
     
     
         8 . The display device of  claim 1 , wherein a side surface of the active pattern is aligned with a side surface of the first opening. 
     
     
         9 . A display device comprising:
 a substrate;   a first conductive layer on the substrate;   a first insulating layer on the first conductive layer;   an active pattern on the first insulating layer and including a semiconductor material;   a second insulating layer on the active pattern; and   a second conductive layer on the second insulating layer,   wherein the first insulating layer has a first opening exposing the first conductive layer,   the second insulating layer has a second opening exposing the first conductive layer,   the first opening is different in breadth from the second opening,   the first opening and the second opening are connected to each other to form one opening, and   the one opening is filled with a material of the second conductive layer.   
     
     
         10 . The display device of  claim 9 , wherein:
 the second conductive layer comprises a first electrode, and   the first electrode is electrically connected to the first conductive layer through the one opening.   
     
     
         11 . The display device of  claim 10 , wherein:
 the second insulating layer has a third opening on the active pattern, and   the first electrode is electrically connected to the active pattern through the third opening.   
     
     
         12 . The display device of  claim 9 , further comprising:
 a third insulating layer on the active pattern; and   a third conductive layer on the third insulating layer,   wherein no other conductive layer is between the second conductive layer and the third conductive layer in a sectional view.   
     
     
         13 . The display device of  claim 12 , wherein a side surface of the third insulating layer is aligned with a side surface of the third conductive layer. 
     
     
         14 . The display device of  claim 9 , wherein:
 the first conductive layer comprises a conductive pattern overlapping the active pattern,   the second conductive layer comprises a pixel electrode electrically connected to the conductive pattern through the one opening, and   the display device further comprises an emission layer and a common electrode on the pixel electrode.   
     
     
         15 . The display device of  claim 9 , wherein:
 the first conductive layer comprises a data line, and   the second conductive layer comprises a connecting member electrically connected to the data line through the one opening.   
     
     
         16 . The display device of  claim 9 , wherein a side surface of the active pattern is aligned with a side surface of the first opening. 
     
     
         17 . A manufacturing method of a display device, the method comprising:
 forming a first conductive layer on a substrate;   forming a first insulating layer and a semiconductor layer on the first conductive layer;   forming a first mask pattern including a first portion and a second portion having different thicknesses, and having a first opening, on the semiconductor layer;   patterning the first insulating layer and the semiconductor layer by utilizing the first mask pattern as a mask to form a second opening of the first insulating layer;   removing the second portion of the first mask pattern to form a second mask pattern including a part of the first portion and having a thickness less than the thickness of the first portion;   patterning the semiconductor layer by utilizing the second mask pattern as a mask to form a semiconductor pattern;   forming a second insulating layer and a second conductive layer on the semiconductor pattern;   forming a third insulating layer on the second conductive layer; and   forming a third mask pattern on the third insulating layer and patterning the third insulating layer by utilizing the third mask pattern as a mask to form a third opening overlapping the second opening.   
     
     
         18 . The manufacturing method of  claim 17 , wherein:
 the first opening is different in breadth from the second opening, and   in the forming of the third opening, a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.   
     
     
         19 . The manufacturing method of  claim 17 , further comprising:
 forming a third conductive layer on the third insulating layer,   wherein the second opening is different in breadth from the third opening,   in the forming of the third opening, the second opening and the third opening are connected to each other to form one opening, and   the one opening is filled with a material of the third conductive layer.   
     
     
         20 . The manufacturing method of  claim 17 , wherein
 in the forming of the semiconductor pattern by patterning the semiconductor layer, a side surface of the semiconductor pattern is aligned with a side surface of the second opening of the first insulating layer.