Systems and methods for flash stacking

Abstract

A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

What is claimed is: 
     
         1 . A method for producing a microelectronic stack comprising:
 providing a plurality of semiconductor substrates having a first face and a second face forming a body thereof for production of microelectronic components, the plurality of semiconductor substrates each having at least one dielectric region thereon wherein the at least one dielectric region extends from the first face to the second face;   disposing a plurality of conductive metallic traces over the dielectric region in a manner selected from a group consisting of printing, direct imaging, and stenciling wherein each of the conductive metallic traces has at least one corresponding trace on each of the plurality of wafers;   bonding each of the plurality of semiconductor substrates thereby forming a layered stack of wafers, wherein the first face of one of the plurality of wafers is bonded to the second face of another one of the plurality of wafers;   predetermining a plurality of dicing lanes on the stack of semiconductor substrates;   dicing the layered stack of wafers along the predetermined dicing lanes such that the dicing exposes a vertical edge of a stack wherein the exposed vertical edge is formed of the dielectric region and the plurality of conductive metallic traces; and   interconnecting the metallic traces along the vertical edge through electroless plating such that the metallic traces are electronically interconnected through each layer of the stack.   
     
     
         2 . The method of  claim 1  wherein the dielectric region for each of the plurality of semiconductor substrates is a different size and dimension. 
     
     
         3 . The method of  claim 1  wherein the metal used in the electroless plating is selected from a group consisting of nickel, copper, silver, and gold. 
     
     
         4 . The method of  claim 1  wherein an additional element is bonded to an outer surface of the layered stack of semiconductor substrates. 
     
     
         5 . The method of  claim 1 , wherein the distance between the conductive traces on each of the plurality of semiconductor substrates in the layered stack of semiconductor substrates is greater than the thickness of one of the plurality of semiconductor substrates. 
     
     
         6 . The method of  claim 1  further comprising partially removing some dielectric material from the dielectric region in an area proximal to the at least one of the plurality of conductive traces. 
     
     
         7 . The method of  claim 1 , wherein bonding comprises providing a bonding layer on at least one of the plurality of semiconductor substrates and bonding that semiconductor substrate to another of the plurality of semiconductor substrates through the bonding layer. 
     
     
         8 . The method of  claim 1 , wherein at least one of the plurality of metallic traces is a partial trace. 
     
     
         9 . The method of  claim 8 , wherein the partial trace corresponds to another partial trace on a corresponding bonded semiconductor substrate. 
     
     
         10 . The method of  claim 8 , wherein the partial trace corresponds to a regular trace path, wherein the regular trace path is connected to a conductive pad. 
     
     
         11 . The method of  claim 9 , wherein each of the corresponding partial traces correspond to a regular trace path that is connected to a conductive pad. 
     
     
         12 . The method of  claim 1 , wherein the microelectronic stack is configured in a chip scale package format. 
     
     
         13 . The method of  claim 1 , further comprising bathing the microelectric stack in a chemical bath in order to bind metal ions to the semiconductor substrate. 
     
     
         14 . The method of  claim 13 , wherein the metal ions are selected from a group consisting of nickel, silver, copper, and gold. 
     
     
         15 . A chip stack comprising:
 A plurality of thinned semiconductor substrates, with each of the plurality of semiconductor substrates having a first surface and a second surface opposite the first surface and a plurality of side surfaces, wherein at least one side surface is covered by a dielectric material that extends from the first surface to the second surface;   At least one bonding layer disposed between each of the plurality of semiconductor substrates;   a plurality of conductive pads disposed on a first surface of each of the plurality of semiconductor substrates;   a plurality of conductive traces disposed on the first surface, wherein each of the plurality of conductive traces is in electrical contact with at least one of the plurality of conductive pads disposed on the first surface and configured to extend over the dielectric material of the at least one side surface covered by a dielectric material, and wherein each of the plurality of conductive traces has at least one corresponding trace on each of the plurality of thinned semiconductor substrates; and   electroless plated connections at least partially disposed over the dielectric material and configured to connect the plurality of printed conductive traces between each of the plurality of thinned chips with the corresponding trace.   
     
     
         16 . The chip stack of  claim 15  wherein the dielectric material in each of the plurality of thinned semiconductor substrates is configured to have varying sizes and shapes between each of the plurality of thinned semiconductor substrates. 
     
     
         17 . The chip stack of  claim 15  wherein the dielectric material has a CTE similar to that of the plurality of thinned semiconductor substrates. 
     
     
         18 . The chip stack of  claim 17  wherein the dielectric material may be selected from a group consisting of silicon oxide, silicon nitride, aluminum oxide, polyimide, epoxy, elastomer and electrophoretically deposited polymer. 
     
     
         19 . The chip stack of  claim 18  wherein the dielectric material further comprises a plurality of layers wherein at least one layer is organic material. 
     
     
         20 . The chip stack of  claim 18  wherein the dielectric material further comprises a plurality of layers wherein at least one layer is inorganic material. 
     
     
         21 . The chip stack of  claim 15  wherein at least one of the corresponding traces on at least one of the plurality of thinned semiconductor substrates is not connected to a conductive pad. 
     
     
         22 . The chip stack of  claim 15  wherein a top surface of the stack is configured to adapt to a chip scaled package format. 
     
     
         23 . The chip stack of  claim 15  wherein the metal used for the electroless plated connection is selected from a group consisting of nickel, copper, silver, and gold. 
     
     
         24 . The chip stack of  claim 15  wherein the adhesive material between the semiconductor substrates is partially removed an area proximal to at least one conductive trace such that a contact area between the electroless plating and the conductive trace is enlarged.