US2021223360A1PendingUtilityA1

Radar device, signal processor, signal processing method, and mobile object

Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPPriority: Jul 19, 2016Filed: Apr 2, 2021Published: Jul 22, 2021
Est. expiryJul 19, 2036(~10 yrs left)· nominal 20-yr term from priority
G01S 7/038G01S 13/34G01S 7/35G01S 13/87G01S 2013/93271G01S 13/931G01S 13/343G01S 7/354G01S 2013/93272
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Claims

Abstract

To provide a radar device, capable of eliminating the influence based on the local feedthrough in the FMCW radar device. There is provided a radar device including: an oscillator configured to oscillate a local signal; a transmitting antenna configured to emit a transmission signal based on the local signal; a receiving antenna configured to receive a reflected wave in which the transmission signal is reflected from a target; a mixer configured to multiply the reflected wave and the local signal by each other to produce a multiplied signal; and a first shifter provided between the oscillator and the mixer and configured to shift a phase of the local signal.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A radar signal processor, comprising:
 a memory;   chirp control signal circuitry configured to generate a chirp control signal,
 wherein the chirp control signal is used to form a transmission signal which is transmitted to a target which provides a reflected wave from the target; and 
 phase control signal circuitry configured to generate phase control signals for the chirp control signal, 
 wherein the memory receives a beat signal generated from the product of the reflected wave and the chirp control signal and 
 wherein the chirp control signal receives a first phase shift from a first phase control signal of the phase control signal circuitry and the transmission signal receives the first phase shift and a second phase shift from a second phase control signal of the phase control signal circuitry. 
   
     
     
         2 . The radar signal processor according to  claim 1 , wherein the first phase control signal sets a shift amount to a first value at a first-time transmission of the transmission signal and sets the shift amount to a second value at a second-time transmission of the transmission signal. 
     
     
         3 . The radar signal processor according to  claim 2 , wherein the memory stores a value of a difference between the beat signal at the first-time transmission of the transmission signal and the beat signal at the second-time transmission of the transmission signal. 
     
     
         4 . The radar signal processor according to  claim 2 , wherein a difference between the first value and the second value is approximately 180 degrees. 
     
     
         5 . The radar signal processor according to  claim 2 , wherein a difference between the first value and the second value is within a range of 180 degrees±22.5 degrees. 
     
     
         6 . The radar signal processor according to  claim 1 , wherein the chirp signal is a signal whose frequency increases or decreases with time. 
     
     
         7 . The radar signal processor according to  claim 1 , wherein the chirp signal is a signal whose frequency linearly increases or decreases with time. 
     
     
         8 . A radar signal processor, comprising:
 a memory;   chirp control signal circuitry configured to generate a chirp control signal,
 wherein the chirp control signal is used to form a transmission signal which is transmitted to a target which provides a reflected wave from the target; and 
 phase control signal circuitry configured to generate phase control signals for the chirp control signal, 
 wherein the memory receives a beat signal generated from the product of the reflected wave and the chirp control signal, 
 wherein the chirp control signal receives a phase shift from a phase control signal of the phase control signal circuitry, and 
 wherein a frequency of the chirp control signal is multiplied by N times. 
   
     
     
         9 . The radar signal processor according to  claim 8 , wherein the memory stores a value of a difference between the beat signal at a first-time transmission of the transmission signal and the beat signal at a second-time transmission of the transmission signal. 
     
     
         10 . The radar signal processor according to  claim 8 , wherein the phase control signal sets a shift amount to a first value at a first-time transmission of the transmission signal and sets the shift amount to a second value at a second-time transmission of the transmission signal. 
     
     
         11 . The radar signal processor according to  claim 10 , wherein a difference between the first value and the second value is approximately 180 degrees. 
     
     
         12 . The radar signal processor according to  claim 10 , wherein a difference between the first value and the second value is within a range of 180 degrees±22.5 degrees. 
     
     
         13 . The radar signal processor according to  claim 8 , wherein the chirp signal is a signal whose frequency increases or decreases with time. 
     
     
         14 . The radar signal processor according to  claim 8 , wherein the chirp signal is a signal whose frequency linearly increases or decreases with time. 
     
     
         15 . A radar signal processor, comprising:
 a memory;   chirp control signal circuitry configured to generate a chirp control signal,
 wherein the chirp control signal is used to form a transmission signal which is transmitted to a target which provides a reflected wave from the target; and 
 phase control signal circuitry configured to generate phase control signals for the chirp control signal, 
 wherein the memory receives a beat signal generated from the product of the reflected wave and the chirp control signal, 
 wherein the transmission signal receives a phase shift from a phase control signal of the phase control signal circuitry, and 
 wherein a frequency of the transmission signal is multiplied by N times. 
   
     
     
         16 . The radar signal processor according to  claim 15 , wherein the memory stores a value of a difference between the beat signal at a first-time transmission of the transmission signal and the beat signal at a second-time transmission of the transmission signal. 
     
     
         17 . The radar signal processor according to  claim 15 , wherein the first phase control signal sets a shift amount to a first value at a first-time transmission of the transmission signal and sets the shift amount to a second value at a second-time transmission of the transmission signal. 
     
     
         18 . The radar signal processor according to  claim 17 , wherein a difference between the first value and the second value is approximately 180 degrees. 
     
     
         19 . The radar signal processor according to  claim 17 , wherein a difference between the first value and the second value is within a range of 180 degrees±22.5 degrees. 
     
     
         20 . The radar signal processor according to  claim 15 , wherein the chirp signal is a signal whose frequency increases or decreases with time.

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