Array Substrate, Manufacturing Method Thereof, and Display Panel

Abstract

An array substrate and a manufacturing method thereof are provided. The array substrate includes a display pixel area for providing pixel units arranged in an array. The array substrate further includes: a base substrate a first insulating layer, a second insulating layer, and a first conductive pattern layer. The first insulating layer is provided on the base substrate, grooves are provided in the first insulating layer, and the grooves are provided in the display pixel area. The second insulating layer is provided on the first insulating layer, and the second insulating layer is also filled into the grooves. The first conductive pattern layer is provided on the second insulating layer.

1 . An array substrate, comprising a display pixel area configured for providing pixel units arranged in an array, the array substrate further comprising:
 a base substrate;   a first insulating layer, provided on the base substrate, and provided with a first groove in the first insulating layer and in the display pixel area;   a second insulating layer, provided on the first insulating layer and further filled into the first groove; and   a first conductive pattern layer provided on the second insulating layer.   
     
     
         2 . The array substrate according to  claim 1 , wherein the second insulating layer is an organic insulating layer. 
     
     
         3 . The array substrate according to  claim 1 , wherein the first groove exposes the base substrate. 
     
     
         4 . The array substrate according to  claim 1 , wherein the first conductive pattern layer comprises a gate line or a portion of the gate line, and the gate line or the portion of the gate line is configured for the display pixel area. 
     
     
         5 . The array substrate according to  claim 4 , wherein an extension direction of the first groove is parallel to the gate line or overlaps with the gate line in a direction perpendicular to the base substrate. 
     
     
         6 . The array substrate according to  claim 4 , wherein at least one of the pixel units comprises a first transistor, the first transistor comprises a first gate electrode;
 the first gate electrode is on a side of the second insulating layer close to the base substrate, and the first gate electrode is electrically connected to the gate line through a first via hole in the second insulating layer;   the array substrate further comprises a gate connection electrode, wherein the gate connection electrode is between the second insulating layer and the first conductive pattern layer, and the first gate electrode is electrically connected to the gate line through the gate connection electrode.   
     
     
         7 . The array substrate according to  claim 6 , wherein the first transistor further comprises a first source electrode and a first drain electrode, and the array substrate further comprises a data line configured for the display pixel area;
 the first source electrode, the first drain electrode, the data line and the gate connection electrode are in a same layer and made of a same material.   
     
     
         8 . The array substrate according to  claim 7 , wherein the first insulating layer is further provided with a second groove, and an extension direction of the second groove is parallel to the data line or overlaps the data line in a direction perpendicular to the base substrate. 
     
     
         9 . The array substrate according to  claim 8 , wherein the pixel unit further comprises a second transistor;
 the second transistor comprises a second gate electrode, and the second gate electrode is connected to the first source electrode or the first drain electrode of the first transistor.   
     
     
         10 . The array substrate according to  claim 9 , wherein the first insulating layer is further provided with a third groove and a fourth groove;
 the first groove, the second groove, the third groove and the fourth groove are respectively at four sides of the second gate electrode.   
     
     
         11 . The array substrate according to  claim 9 , wherein the first insulating layer is further provided with a third groove, and the third groove is arranged in parallel with the second gate electrode and corresponding to the second gate electrode;
 in a length direction of the third groove, a length of the third groove is greater than a length of the second gate electrode.   
     
     
         12 . The array substrate according to  claim 9 , wherein the second transistor comprises a second source electrode and a second drain electrode, and the array substrate further comprises a third insulating layer;
 in the direction perpendicular to the base substrate, the second source electrode and the second drain electrode are between the second insulating layer and the first conductive pattern layer;   in the direction perpendicular to the base substrate, the third insulating layer is between the first conductive pattern layer and the second source electrode as well as the second drain electrode.   
     
     
         13 . The array substrate according to  claim 12 , further comprising a fourth insulating layer and a pixel electrode laminated on the first conductive pattern layer,
 wherein the second source electrode or the second drain electrode is electrically connected to the pixel electrode through a second via hole in the fourth insulating layer.   
     
     
         14 . The array substrate according to  claim 11 , wherein the first conductive pattern layer further comprises a driving connection electrode;
 the second source electrode or the second drain electrode is connected to the pixel electrode through the driving connection electrode.   
     
     
         15 . The array substrate according to  claim 6 , further comprising a first capacitor electrode,
 wherein in a direction perpendicular to the base substrate, the first capacitor electrode is disposed between the first insulating layer and the second insulating layer.   
     
     
         16 . The array substrate according to  claim 15 , further comprising a second capacitor electrode,
 wherein the second capacitor electrode is in a same layer as the first gate electrode and directly faces the first capacitor electrode to form a capacitor.   
     
     
         17 . A display panel comprising the array substrate according to  claim 1 . 
     
     
         18 . A method for manufacturing an array substrate, the array substrate comprising a display pixel area for providing pixel units arranged in an array,
 wherein the manufacturing method comprises:
 providing a base substrate; 
 forming a first insulating layer on the base substrate, and forming a first groove in the first insulating layer and in the display pixel area; 
 forming a second insulating layer on the first insulating layer, wherein the second insulating layer is further filled into the first groove; and 
 forming a first conductive pattern layer on the second insulating layer. 
   
     
     
         19 . The manufacturing method according to  claim 18 , wherein the first insulating layer is an organic insulating layer. 
     
     
         20 . The manufacturing method according to  claim 18 , wherein forming the first conductive pattern layer comprises:
 forming a gate line for the display pixel area or forming a portion of the gate line configured for the display pixel area.