Results processing circuits and methods associated with computational memory cells

Abstract

A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

1 . A method for response for a processing device, the method comprising:
 generating a computation result using a processing array device having a plurality of memory cells arranged in an array having a plurality of columns and a plurality of rows, each memory cell having a storage element wherein the array has a plurality of sections and each section has a plurality of bit line sections and a plurality of bit lines with one bit line per bit line section, wherein the memory cells in each bit line section are all connected to a single read bit line that generates the computation result and the plurality of bit lines in each section are distinct from the plurality of bit lines included in the other sections of the array;   communicating, using a plurality of RSP data lines of the processing array device, a combined computation result; and   performing an response (RSP) read operation by engaging in stages the plurality of RSP data lines.   
     
     
         2 . The method of  claim 1  further comprising initiating a read operation without using the RSP data lines in any clock cycle after the RSP read operation is initiated without affecting the combined computation result. 
     
     
         3 . The method of  claim 1  further comprising driving an RSP result on the plurality of RSP data lines out of the processing array. 
     
     
         4 . The method of  claim 3 , wherein driving the RSP result further comprises initiating a read operation that causes a “1” computation result to be captured in a read storage of each bit line section and setting each of a first stage of the plurality of RSP data line stages to a default state. 
     
     
         5 . The method of  claim 4 , wherein, after initiating the read operation and setting each of the first stage of the plurality of RSP data line stages to a default state, driving the RSP result further comprises engaging RSP outbound circuits in each of the first stage of the plurality of RSP data line stages and causing each of the first stage of the plurality of RSP data line stages to store a value of “1”. 
     
     
         6 . The method of  claim 5 , wherein, after engaging the RSP outbound circuits in each of the first stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a second stage of the plurality of RSP data line stages, causing each of the second stages of the plurality of RSP data line stages to store a value of “1” and causing each of the first stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         7 . The method of  claim 6 , wherein, after engaging the RSP outbound circuits in each of the second stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a third stage of the plurality of RSP data line stages, causing each of the third stage of the plurality of RSP data line stages to store a value of “1” and causing each of the second stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         8 . The method of  claim 7 , wherein, after engaging the RSP outbound circuits in each of the third stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a fourth stage of the plurality of RSP data line stages, causing each of the fourth stage of the plurality of RSP data line stages to store a value of “1” and causing each of the third stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         9 . The method of  claim 8 , wherein, after engaging the RSP outbound circuits in each of a fourth stage of the plurality of RSP data line stages, disengaging the outbound RSP circuits and causing each of the fourth stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         10 . The method of  claim 1  further comprising engaging the RSP data lines to produce and store a result for a first stage of the plurality of RSP data line stages in each bit line section. 
     
     
         11 . The method of  claim 10 , wherein storing the result further comprises initiating a read operation that causes a “1” computation result to be captured in a read storage of each bit line section and setting each of a first stage of the plurality of RSP data line stages to a default state. 
     
     
         12 . The method of  claim 11 , wherein, after initiating the read operation and setting each of the first stage of the plurality of RSP data line stages to a default state, driving the RSP result further comprises engaging RSP outbound circuits in each of the first stage of the plurality of RSP data line stages and causing each of the first stage of the plurality of RSP data line stages to store a value of “1”. 
     
     
         13 . The method of  claim 12 , wherein, after engaging the RSP outbound circuits in each of the first stage of the plurality of RSP data line stages, disengaging the RSP outbound circuits, engaging RSP inbound circuits and initiating a write operation that stores a state of the first stage RSP data line in the computational memory cell in the bit line section. 
     
     
         14 . The method of  claim 13 , wherein, after initiating the write operation, disengaging the RSP inbound circuits causing the first stage RSP data line to return to a default value. 
     
     
         15 . The method of  claim 1  further comprising engaging the RSP data lines to produce and store a result for a second stage of the plurality of RSP data line stages in each bit line section. 
     
     
         16 . The method of  claim 15 , wherein storing the result further comprises initiating a read operation that causes a “1” computation result to be captured in a read storage of each bit line section and setting each of a first stage of the plurality of RSP data line stages to a default state. 
     
     
         17 . The method of  claim 16 , wherein, after initiating the read operation and setting each of the first stage of the plurality of RSP data line stages to a default state, driving the RSP result further comprises engaging RSP outbound circuits in each of the first stage of the plurality of RSP data line stages and causing each of the first stage of the plurality of RSP data line stages to store a value of “1”. 
     
     
         18 . The method of  claim 17 , wherein, after engaging the RSP outbound circuits in each of the first stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a second stage of the plurality of RSP data line stages, causing each of the second stages of the plurality of RSP data line stages to store a value of “1” and causing each of the first stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         19 . The method of  claim 18 , wherein, after engaging the RSP outbound circuits in each of the second stage of the plurality of RSP data line stages, disengaging the RSP outbound circuits, engaging RSP inbound circuits and initiating a write operation that stores a state of the first stage RSP data line in the computational memory cell in the bit line section. 
     
     
         20 . The method of  claim 19 , wherein, after initiating the write operation, disengaging the RSP inbound circuits causing the first stage RSP data line to return to a default value. 
     
     
         21 . The method of  claim 1  further comprising engaging the RSP data lines to produce and store a result for a third stage of the plurality of RSP data line stages in each bit line section. 
     
     
         22 . The method of  claim 21 , wherein storing the result further comprises initiating a read operation that causes a “1” computation result to be captured in a read storage of each bit line section and setting each of a first stage of the plurality of RSP data line stages to a default state. 
     
     
         23 . The method of  claim 22 , wherein, after initiating the read operation and setting each of the first stage of the plurality of RSP data line stages to a default state, driving the RSP result further comprises engaging RSP outbound circuits in each of the first stage of the plurality of RSP data line stages and causing each of the first stage of the plurality of RSP data line stages to store a value of “1”. 
     
     
         24 . The method of  claim 23 , wherein, after engaging the RSP outbound circuits in each of the first stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a second stage of the plurality of RSP data line stages, causing each of the second stages of the plurality of RSP data line stages to store a value of “1” and causing each of the first stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         25 . The method of  claim 24 , wherein, after engaging the RSP outbound circuits in each of the second stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a third stage of the plurality of RSP data line stages, causing each of the third stage of the plurality of RSP data line stages to store a value of “1” and causing each of the second stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         26 . The method of  claim 25 , wherein, after engaging the RSP outbound circuits in each of the third stage of the plurality of RSP data line stages, disengaging the outbound RSP circuits and causing each of the first and second stage of the plurality of RSP data line stages to be set to “1” and engaging the RSP inbound circuits. 
     
     
         27 . The method of  claim 26 , wherein, after disengaging the RSP outbound circuits and engaging the inbound RSP circuits, initiating a write operation that stores a state of the first stage RSP data line in the computational memory cell in the bit line section. 
     
     
         28 . The method of  claim 27 , wherein, after initiating the write operation, disengaging the RSP inbound circuits causing the first stage RSP data line to return to a default value. 
     
     
         29 . The method of  claim 1 , wherein engaging the RSP data lines to produce and store a result for a fourth stage of the plurality of RSP data line stages in each bit line section. 
     
     
         30 . The method of  claim 29 , wherein engaging the RSP data lines further comprises initiating a read operation that causes a “1” computation result to be captured in a read storage of each bit line section and setting each of a first stage of the plurality of RSP data line stages to a default state. 
     
     
         31 . The method of  claim 30 , wherein, after initiating the read operation and setting each of the first stage of the plurality of RSP data line stages to a default state, driving the RSP result further comprises engaging RSP outbound circuits in each of the first stage of the plurality of RSP data line stages and causing each of the first stage of the plurality of RSP data line stages to store a value of “1”. 
     
     
         32 . The method of  claim 31 , wherein, after engaging the RSP outbound circuits in each of the first stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a second stage of the plurality of RSP data line stages, causing each of the second stages of the plurality of RSP data line stages to store a value of “1” and causing each of the first stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         33 . The method of  claim 32 , wherein, after engaging the RSP outbound circuits in each of the second stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a third stage of the plurality of RSP data line stages, causing each of the third stage of the plurality of RSP data line stages to store a value of “1” and causing each of the second stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         34 . The method of  claim 33 , wherein, after engaging the RSP outbound circuits in each of the third stage of the plurality of RSP data line stages, engaging the RSP outbound circuits in each of a fourth stage of the plurality of RSP data line stages, causing each of the fourth stage of the plurality of RSP data line stages to store a value of “1” and causing each of the third stage of the plurality of RSP data line stages to return back to a default state. 
     
     
         35 . The method of  claim 34 , wherein, after engaging the RSP outbound circuits in each of a fourth stage of the plurality of RSP data line stages, disengaging the outbound RSP circuits and causing each of the first, second and third stage RSP data lines to be set to “1” and engaging the inbound RSP circuits. 
     
     
         36 . The method of  claim 35 , wherein, after disengaging the RSP outbound circuits and engaging the inbound RSP circuits, initiating a write operation that stores a state of the first stage RSP data line in the computational memory cell in the bit line section. 
     
     
         37 . The method of  claim 36 , wherein, after initiating the write operation, disengaging the RSP inbound circuits causing the first, second and third stage RSP data line to return to a default value.